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1881M
Theory of Operation
4. Operating Instructions
4.1 General Operation
4.1.1 Overview
The operation of the 1881M can be divided into four phases. The first phase includes all the setup
necessary before the 1881M ADC can successfully be used. This includes installation of the module and
programming the control registers. The module will not accept gates until the control registers have been
programmed. Once all the setup is complete, the module is in acquisition mode and ready to accept a gate.
Upon the end of the gate, conversion is initiated The charges are digitized and those above the pre-
programmed sparsification threshold are written into the data buffer. While the inputs are being converted,
the Conversion In Progress (CIP) signal is true. The user can begin the final phase and readout after the
conversion has finished.
4.1.2 Setup
As per the FASTBUS specification, the 1881M may be inserted in the FASTBUS crate with the power
either on or off. No special precautions are required when attaching the front panel connectors. If it is desired
to daisy chain the GATE or CLR signals, the jumpers connecting the terminations for these signals must
be removed on all except the last unit in the daisy chain. A minimum of three CSR registers must be
programmed to establish a working condition in the 1881M: CSR0, CSR1, & CSR7. CSR0: CSR0 <1>
must be set if logical addressing is used. CSR1: CSR1 contains most of the configuration bits for the
module. The default selection will be: no sparsification, front panel gate and a 14 µs fast clear window.
CSR3: CSR3 is being used. CSR7 : This register must be configured if it is desired to use class N
broadcasts. After the CSR registers are programmed, the unit is ready to acquire data.
4.1.3 Acquisition
Acquisition begins with the arrival of a gate signal. The charge received on all 64 channels during the gate
is integrated. Charge arriving after the end of the gate is not included. Charge integration begins 20 ns
(nominal) after the leading edge of the gate signal.
The trailing edge of the gate signal begins the Fast Clear Window (FCW). During this period the
integrated charge is digitized. Conversion In Progress (CIP) is true until the conversion is complete and the
FCW has expired. The length of the FCW can be controlled either by TR5 on the FASTBUS backplane
or CSR1 <27:24> (TR5 can be controlled with the 1810 CAT). During the FCW, a Fast Clear may be
issued to abort the event. Data which is already buffered is simply written over by the next event.
4.1.4 Buffering and Readout
The buffer memory of the 1881M consists of 32-bit words. This memory is partitioned into 64 pages of
128 locations each. Each page can store the data from one event. Two pointers are maintained by the
1881M. The Read pointer is the location of data word to be read by the FASTBUS and the Write pointer
is the location for storing the next data word from the front end. These pointers implement a FIFO for
events (pages) and for data words.
4.1.5 Read and Write Pointers
Because of the partitioning of the memory both pointers break down into two bit fields. Bits <12:7>
identify the page number and bits <6:0> specify a word location inside a buffer. When a pointer advances
to the next data word it is incremented by one. When the pointer is advanced to the next page, the page
number is incremented, perhaps rolling over, and the word location is set to zero.
4-1
July 23, 1998
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