Block Diagram - NXP Semiconductors UM11712 User Manual

NXP Semiconductors
Figure 1. The PCAL6534EV-ARD board picture, top view (up) and bottom view (down)

4.3 Block diagram

UM11712
User manual
Figure 2 shows a block diagram of the PCAL6534EV-ARD daughter board. Alongside
the DUT (U1), the board includes a series of peripherals that assures the operation of the
board. U1 is linked to Arduino interface (J1 to J4) through two busses: the I
the control bus.
The port P0 and P1 (8-bit wide each) controls the four-digit LED display (D13 to D16)
located on the board, through the MAX V CPLD which acts as display decoder/driver. All
16 I/O lines are shared with the 16 BIT I/O PORT (J6).
The port P2 (8-bit wide) is shared with the on-board user LEDs D4 to D11, and the 8 BIT
I/O PORT (J7)
Th first five LSB I/O lines of the port P3 (8-bit wide) are linked to the 10 BIT I/O PORT
(J8) only. The remaining tree lines of P3 and the port P4 (2-bit wide) are shared with on-
board user switches (SW1 to SW4) and the 10 BIT I/O PORT (J8).
The board contains two LDO voltage regulators, for 3.3 V (U3) and 1.8 V (U4), power
rails.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 31 January 2022
UM11712
PCAL6534EV-ARD evaluation board
© NXP B.V. 2022. All rights reserved.
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C-bus and
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