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UM11665
SC18IS604-EVB evaluation board
Rev. 1.0 — 19 August 2021
Document information
Information
Content
Keywords
SC18IS604, SC18IS600, SPI to I
Abstract
SC18IS604 is designed to serve as an interface between the standard SPI
of a host and the serial I
with other I
2
C, I
2
C-bus. This allows the host to communicate directly
2
C-bus devices.
2
2
C Controller, I
C bridge, SPI bridge
User manual
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Summary of Contents for NXP Semiconductors UM11665
- Page 1 UM11665 SC18IS604-EVB evaluation board Rev. 1.0 — 19 August 2021 User manual Document information Information Content Keywords SC18IS604, SC18IS600, SPI to I C, I C Controller, I C bridge, SPI bridge Abstract SC18IS604 is designed to serve as an interface between the standard SPI of a host and the serial I C-bus.
- Page 2 UM11665 NXP Semiconductors SC18IS604-EVB evaluation board Revision history Date Description v.1.0 20210819 Initial version UM11665 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. User manual Rev. 1.0 — 19 August 2021...
- Page 3 UM11665 NXP Semiconductors SC18IS604-EVB evaluation board Important notice NXP provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals.
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Page 4: Introduction
SC18IS604-EVB evaluation board in the users’ hardware platform. Finding kit resources and information on the NXP web site NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://www.nxp.com. The information page for SC18IS604-EVB evaluation board is at http://www.nxp.com/... -
Page 5: Headers And Jumpers
UM11665 NXP Semiconductors SC18IS604-EVB evaluation board C slave devices can be accessed directly by the SPI master via the SC18IS604 SPI to C bridge. 4.1 Headers and jumpers Please refer to Figure 1 to find the location of connectors and jumpers on the SC18IS604-EVB evaluation board. -
Page 6: Schematic, Board Layout And Bill Of Materials
UM11665 NXP Semiconductors SC18IS604-EVB evaluation board Table 3. JP4 - I2C header JP4 – I2C Header Function GROUND Table 4. JP2 - GPIO JP2 – GPIO Function GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GROUND 4.3 Schematic, board layout and bill of materials The schematic, board layout and bill of materials for the SC18IS604-EVB evaluation board are available at http://www.nxp.com/SC18IS604-EVB. -
Page 7: I2C Clock Configuration
UM11665 NXP Semiconductors SC18IS604-EVB evaluation board 4.4.5 I C clock configuration 0x20 0x02 0x05 // Set I2C clock to 375KHz 4.4.6 Device ID read 0x50 0xFE // Read device ID into buffer 0x06 0xff 0xff …… 0xff // read 16 bytes from buffer, return data 0x53 // 0x43 0x31 0x38 0x49 0x53.. -
Page 8: Legal Information
6.1 Definitions and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this Draft —... - Page 9 UM11665 NXP Semiconductors SC18IS604-EVB evaluation board Tables Tab. 1. Jumper settings ..........5 Tab. 4. JP2 - GPIO ............6 Tab. 2. JP1 - SPI header ..........5 Tab. 5. Errata list ............7 Tab. 3. JP4 - I2C header ..........6 Figures Fig.
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Page 10: Table Of Contents
'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 August 2021 Document identifier: UM11665...
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