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NXP Semiconductors
4.7 Control bus
4.8 I/O bus
Table 2. The I/O allocation table
PCAL6534
Direction
(U1) pin
P0_0
I/O
P0_1
I/O
P0_2
I/O
P0_3
I/O
P0_4
I/O
P0_5
I/O
P0_6
I/O
P0_7
I/O
P1_0
I/O
P1_1
I/O
P1_2
I/O
P1_3
I/O
P1_4
I/O
UM11712
User manual
The control bus manages RESET, ADDR, and INT pins of the PCAL6534 IC. The
RESET pin is digital input and is controlled by the system host. Its role is to reset the I/
O expander when a time-out or other improper operation occurs. Asserting a low level of
this line forces a reset operation of the internal control section of the IC (puts the internal
registers in their default state and forces a reinitialization of the I
the same manner as power-on sequence). The RESET pin is controlled by the EVK
motherboard through J3-1 (ARDUINO port).
The ADDR pin is digital input and represents a programmable hardware address
package which can be asserted low or high, to assign two different slave addresses. The
input is controlled by the EVK through J3-2 (Arduino port).
The INT pin is an open-drain interrupt output, activated when any input state differs from
its corresponding input port register state, indicating to the host system that an input
state has changed. The line is monitored by the EVK through J3-3 ARDUINO port and
locally by the LED (D3) located on the daughterboard. The LED D3 can be deactivated
by removing JP1 jumper. When D3 is inactive (JP1 removed) the open-drain is polarized
through R42. R42 also has the role to compensate the voltage drop of D3 assuring 3.3V
high level in high state of the interrupt line (see SPF-46656.pdf schematic file).
The PCAL6534 IC contains 34 configurable I/O pins, organized in five ports, P0 to P4.
The ports P0 to P3 are 8-bit wide, while P4 is 2-bit wide. P0 and P1 are allocated to the
four-digit LED display (through MAX V CPLD, U2). The port P2 drives the on-board LEDs
(D4 to D11). The on-board user switches SW1 to SW5 are connected to port P3 and P4.
From port P3 the last MSB three lines are allocated to the on-board switches. All I/O lines
of the PCAL6534 IC are linked to the I/O port connectors for external access of the I/
O lines (see the schematic of the daughterboard).
PCAL6534 I/O lines (U1).
CPLD
LED
(U2) pin
IO_9
-
IO_10
-
IO_11
-
IO_12
-
IO_13
-
IO_14
-
IO_15
-
IO_16
-
IO_17
-
IO_18
-
IO_19
-
IO_22
-
IO_23
-
All information provided in this document is subject to legal disclaimers.
16 BIT – I/
Switch
O PORT (J6)
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
Rev. 1.0 — 31 January 2022
UM11712
PCAL6534EV-ARD evaluation board
2
C state machine, in
Table 2
shows the allocation of the
8 BIT – I/O
PORT (J7)
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2022. All rights reserved.
10 BIT – I/
O PORT (J9)
-
-
-
-
-
-
-
-
-
-
-
-
-
9 / 31
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