Table of Contents
Advertisement
6. About Hardware
Delay time at the time of output
Output width at the time of output
Internalclk
TRG (Output)
used as internal clock output
Figure 6.4. Timing for External Samplicg Clock
Figure 6.5. Timing for External Trigger Input Signal
Table 6.2. Timing Table of External Control Signals
Delay time from external trigger input signal until A/D conversion start pulse
*1.
Set up time of external trigger input signal (Rising edge)
Hold time of external trigger input signal (Rising edge)
Set up time of external trigger input signal (Falling edge)
Hold time of external trigger input signal (Falling edge)
Delay time until internal clock in output to external trigger output signal
Period when internal clock is maintained to "H" (When pulse output is set) *3
Period when internal clock is maintained to "H" (When pulse output is not set)
*3
*1 It is the delay time when internal clock is used.
When digital filter is being used, the delay time is added by 50ns.
*2 1nsec is 1/1,000,000,000 seconds.
*3 The internal clock less than 100nsec cannot be output.
And it is always maintained to "H"at 100nsec.
CAUTION
All the model values are shown at the time of Table 6.2.
64
t
OP
t
OD
Parameter
Symbol
Time (Unit)
t
5nsec *2
DEC1
t
10nsec
SRS
t
10nsec
HRS
t
10nsec
SFS
t
10nsec
HRS
t
35nsec
OD
t
50nsec
OP
t
10nsec
OP
DIG-100M1002-PCI
Advertisement
Table of Contents
