Timing For Control Signal; Timing For Control Signal Of Analog Input Function - Contec DIG-100M1002-PCI User Manual

Timing for Control Signal

Timing for Control Signal of Analog Input Function

DIG-100M1002-PCI is unrelated with the sampling clock, it is always sampled in each 10nsec. In a
word, the conversion results from the A/D convertor are stored in an internal register once, the values
are updated in each 10nsec.
The sampling clock controls the timing that the conversion results are stored from this register to an
internal memory. Only the input data which is in memory can be acquired as effective data.
Therefore, the following things are caused by a time position relationship between the sampling clock
and 10nsec. When the sampling clock is input immediately after updating register, the error at time is
not caused. However, when the sampling clock is input immediately before updating register, because
the result which is updated by last time is stored in the internal register, the error between the sampling
clock and the sampled timing is 10nsec or less.
Clock （10nsec）
A/D converter output
Register
Sampling clock
Memory
Figure 6.2. The sampling action is detailed
Figure 6.3, 6.4, 6.5 and Table 6.2 shows the timing for control signal of analog input function.
Delay time at the time of input
TRG (input)
used as pre-trigger
ADC ConverSionStart
Figure 6.3. Delay time when an external trigger input signal was used
DIG-100M1002-PCI
A B
X
X A B
－
t
DEC1
C D E
C D E
B
6. About Hardware
F G H
F G H
D G
I
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