Quectel EG91 Series Hardware Design page 49
Lte standard module
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Also See for EG91 Series:
- Hardware design (98 pages) ,
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RTS
37
DTR
30
TXD
35
RXD
34
Table 12: Pin Definition of Debug UART Interface
Pin Name
Pin No.
DBG_TXD
23
DBG_RXD
22
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if your application
is equipped with a 3.3 V UART interface. A voltage-level translator TXS0108EPWR provided by Texas
Instruments is recommended. The following figure shows a reference design.
Visit http://www.ti.com for more information.
Another example with transistor translation circuit is shown as below. For the design of circuits shown in
dotted lines, see that shown in solid lines, but please pay attention to the direction of connection.
EG91_Series_Hardware_Design
DI
Request to send
Data terminal ready
DI
Sleep mode control
DO
Transmit
DI
Receive
I/O
Description
DO
Debug UART transmit
DI
Debug UART receive
Figure 20: Reference Circuit with Translator Chip
LTE Standard Module Series
Comment
1.8 V power domain.
If unused, keep it open.
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