Quectel EG91 Series Hardware Design page 30
Lte standard module
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Also See for EG91 Series:
- Hardware design (98 pages) ,
- Hardware design (94 pages) ,
- Hardware design (109 pages)
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DCD
38
CTS
36
RTS
37
DTR
30
TXD
35
RXD
34
Debug UART Interface
Pin
Pin Name
No.
DBG_TXD
23
DBG_RXD
22
PCM Interface
Pin
Pin Name
No.
PCM_DIN
6
PCM_DOUT
7
PCM_SYNC
5
PCM_CLK
4
I2C Interface
EG91_Series_Hardware_Design
DO
Data carrier detect
DO
Clear to send
DI
Request to send
Data terminal ready
DI
Sleep mode control
DO
Transmit
DI
Receive
I/O
Description
Debug UART
DO
transmit
Debug UART
DI
receive
I/O
Description
DI
PCM data input
DO
PCM data output
PCM data frame
DIO
sync
DIO
PCM data clock
LTE Standard Module Series
V
min = 1.35 V
If unused, keep it open.
OH
V
min = -0.3 V
IL
1.8 V power domain.
V
max = 0.6 V
IL
Pulled up by default.
V
min = 1.2 V
IH
Low level wakes up the
V
max = 2.0 V
IH
module.
If unused, keep it open.
V
max = 0.45 V
OL
V
min = 1.35 V
OH
1.8 V power domain.
V
min = -0.3 V
IL
If unused, keep it open.
V
max = 0.6 V
IL
V
min = 1.2 V
IH
V
max = 2.0 V
IH
DC
Comment
Characteristics
V
max = 0.45 V
OL
V
min = 1.35 V
OH
1.8 V power domain.
V
min = -0.3 V
IL
If unused, keep it open.
V
max = 0.6 V
IL
V
min = 1.2 V
IH
V
max = 2.0 V
IH
DC
Comment
Characteristics
V
min = -0.3 V
IL
V
max = 0.6 V
IL
V
min = 1.2 V
1.8 V power domain.
IH
V
max = 2.0 V
If unused, keep it open.
IH
V
max = 0.45 V
OL
V
min = 1.35 V
OH
V
max = 0.45 V
1.8 V power domain. In
OL
V
min = 1.35 V
master mode, it is an
OH
V
min = -0.3 V
output signal. In slave
IL
V
max = 0.6 V
mode, it is an input
IL
V
min = 1.2 V
signal.
IH
V
max = 2.0 V
If unused, keep it open.
IH
29 / 105
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