Quectel EG91 Series Hardware Design page 38

Figure 7: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low
ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC
array, and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an
external application has to be a single voltage source and can be expanded to two sub paths with star
structure. The width of VBAT_BB trace should be no less than 1 mm, and the width of VBAT_RF trace
should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to avoid the damage caused by electric surge and ESD, it is suggested that a TVS
diode with low reverse stand-off voltage V
pulse current I should be used. The following figure shows the star structure of the power supply.
PP
VBAT
+
D1 C1
100 μF
WS4.5D3HV
EG91_Series_Hardware_Design
(4.5 V), low clamping voltage V
RWM
C5
C4
C2 C3
100 nF 33 pF 10 pF 100 μF
Figure 8: Star Structure of Power Supply
LTE Standard Module Series
+
C6 C7 C8
100 nF 33 pF 10 pF
and high reverse peak
C
VBAT_RF
VBAT_BB
Module
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