EKE-Electronics CVB1621A Technical Manual page 39

Address Contents
0x85 VME and Z80 Interrupt Status register
Bit 7: not used
Bit 6: Zilog CPU INT1\ active, generated from VME (same as Bit 1)
0= Not active
1= Interrupt pending
Bit 5: VMEbus interrupt output active
0= Not active
1= Interrupt active (not yet cleared by VMEbus interrupt acknowledge cycle
Bit 4,3: not used
Bit 2: Zilog CPU INT2\ active / pending
0= Not active
1= Interrupt pending
Bit 1: Zilog CPU INT1\ active / pending (Same as Bit 6)
0= Not active
1= Interrupt pending
Bit 0: Zilog CPU INT0\ active / pending
0= Not active
1= Interrupt pending
This bit is always read as 0 thus Zilog CPU INT0\ is not used.
0x90 CVB Control register
Bit 7,6: not used
Bit 5: DCDC converter enable, Channel B
0= Disabled (Default). If DCDCOK status is ERROR, clearing this bit also
restores status to OK.
1= Enabled
Bit 4: Release/Reset SJA1000 of Channel B
0= SJA1000 in reset
1= SJA100 released from reset
Bit 3,2: not used
Bit 1: DCDC converter enable, Channel A
0= Disabled (Default). If DCDCOK status is ERROR, clearing this bit also
restores status to OK.
1= Enabled
Bit 0: Release/Reset SJA1000 of Channel A
0= SJA1000 in reset
1= SJA100 released from reset
CVB1621A and CVB2456A Technical Manual, ver. 3.00
Command line interface
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