EKE-Electronics CVB1621A Technical Manual page 38

Command line interface
Address Contents
0x82 Ctrl_B register
Bit 7: Zilog CPU INT2\ test.
0= Normal operation (Default)
1= Force INT2\ active
Bit 6: Zilog CPU INT1\ test.
0= Normal operation (Default)
1= Force INT1\ active
Bit 5: Clear Zilog CPU INT1\ generated from VMEbus.
0= No effect to interrupt (Default)
1= Clear. After set to 1, bit is automatically cleared to 0
Bit 4: Generate VMEbus interrupt output
0= No effect to interrupt (Default)
1= Generate interrupt. After set to 1, bit is automatically cleared to 0.
(Interrupt it self is cleared only by VMEbus interrupt acknowledge cycle.)
Bit 3: Refresh watchdog automatically by FPGA.
0= Require manual refresh with WDKICK –bit. (Default)
1= Active
Bit 2: Zilog CPU INT2\ enable.
0= Disabled (Default)
1= SJA1000 interrupt outputs generate INT2\
Bit 1: Zilog CPU INT1\ enable.
0= Disabled (Default)
1= VMEbus interrupt in generate INT1\
Bit 0: Refresh watchdog.
0= No effect to refresh pulse output (Default)
1= Generate refresh pulse to external watchdog device. After set to 1, bit
is automatically cleared to 0.
0x84 System Status register
Bit 7: ACFAIL~ input from VMEbus active
0= Not active (Normally)
1= Active
Bit 6: SYSFAIL~ input from VMEbus active
0= Not active (Normally)
1= Active. If Bit 2 in CTRLA register is active, this should also be active.
Bit 5,4,3,2,1: not used
Bit 0:Emulator jumper installed
0= Installed.
1= Not installed (Normal operation)
Jumper is installed to connector X6, shorting pins 9 and 10. When jumper
is installed, watchdog is refreshed automatically by FPGA, and software
can start in test–mode.
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CVB1621A and CVB2456A Technical Manual, ver. 3.00