EKE-Electronics CVB1621A Technical Manual page 10

Overview of the CVB
The Host CPU (enhanced Z180 microprocessor) combines a high-performance CPU
core with a variety of system and resources useful in a broad range of applications. The
CPU core consists of five functional blocks:
Clock generator, which generates the system clock from an external crystal or clock
input bus state controller
Bus State Controller, which performs all the status and bus-control activity
associated with CPU and some on-chip peripherals.
Interrupt controller, which monitors and prioritises the variety of internal and
external interrupts and traps to provide the correct responses from the CPU.
Memory Management Unit (MMU), which allows the user to map the memory used
by the CPU into the 1-MB addressing range supported by the Z180 CPU.
Central processing Unit (CPU) is microcopy to provide a core that is the object-code
compatible with the Z180 CPU
The integrated I/O resources make up the remaining four functional blocks:
Direct Memory Access controller (DMA, 2 channels), which provide
Programmable Reload Times (PRT), which consists of two separate channels,
each containing a 16-bit counter (timer) and count reload registers.
Asynchronous Serial Communication Interface (ASCI) which provide two
full-duplex UARTs. Each channel includes a programmable baud rate generator
and modem control signals.
Clock Serial I/O channel (CSI/O).
The two CAN Controllers (SJA 1000) for both CAN busses (A and B) have:
Reception and transmission of standard and extended frame format messages
Receive First In-First Out (FIFO, 64-byte) queue process technique
Error counter switch read/write access
Programmable error warning limit
Last error code register
Error interrupt for each CAN bus error
Single shot transmission (no re-transmission on error or arbitration lost)
Listen only mode (monitoring the CAN bus, no acknowledge, no error flags)
6
CVB1621A and CVB2456A Technical Manual, ver. 3.00