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DP-4X AUDIO VIDEO MUTE CIRCUIT EXPLANATION
(See DP-4X Series Chassis Audio Video Mute Circuit Diagram for details)
There are times in which the main picture and audio must be muted. This can be because of changing channels,
Auto Programming and Power On/Off where the noise between stations or Audio pop is unacceptable. Another
situation is when the deflection circuit malfunctions. All this is done primarily to prevent damage to the CRTs or
to external amplifiers or speakers connected to the projection television.
VIDEO MUTE ACTIVATION: (Described Later)
There are 4 Inputs to the Mute Activation Circuit comprised of QY57, and QY48.
1.
V Mute from the Microprocessor I004 pin 49.
2.
Spot from the Deflection PWB PDS2 pin 4.
3.
H. Blk Loss Detection from QY58.
4.
AC Loss Detection from QY47.
The following action is called MUTE ACTIVATION from this point forward, please use the below explanation
when Mute Activation is mentioned so it will not have to be repeated when explaining the V. Mute 2 circuits.
MUTE ACTIVATION:
Any High to the base of QY57 will turn this transistor on. The collector goes low and pulls the base of
QY48 low turning it on. QY48 emitter is connected to the SW 9.3V line through DY08. When QY48 turns
on, it's collector goes high and this high is routed to the following circuits.
1.
RGB PROCESSOR MUTE:
Through RZ41, DY05, and RZ09 and into the Rainforest IC IY04 pin 39. This pin is also the same
pin that FC H Blk and FC V Blk is input. Generally this input is a positive going pulse that blanks
the video during the peak pulses which represent retrace. However, when the DC component is
forced high by the action of QY48 turning on, this pin goes high and mutes the output of RGB.
2.
V MUTE 2:
Another route for the high from QY48 is to the base of QY42. This transistor turns on and the high
from its emitter. This High is labeled V MUTE 2 and is described later.
(1) V MUTE: From Pin 49 of the Microprocessor I004
When its necessary to mute the audio and video as described in the first paragraph, the Microprocessor outputs a
High from pin 49. This high is routed to the Mute Activation Circuit (QY57 base) as previously described.
(2) SPOT:
Another circuit attached to the Mute Activation circuit (QY57 base) is SPOT. This signal is generated from the
deflection PWB when either Horizontal or Vertical deflection is lost. This is to prevent a horizontal or vertical
line from being burnt into the CRTs. See Horizontal and Vertical Sweep Loss Detection circuit and explanation
and circuit diagram for details. This high is input from PDS2 pin (4), through DY12 to the base of QY57. See
the Mute Activation Circuit (QY57 base) explained previously.
(3) H BLK LOSS DETECTION:
Another circuit attached to the Mute Activation circuit (QY57 base) is H Blk Loss Det.
If the Horizontal Blanking signal is loss to the Signal PWB, QY59 will detect the loss. H. Blk is provided from
the Deflection PWB through the PDS2 pin (8). Then to the base of QY59. By the activity of the pulse charging
CY99 and CY98, the base of QY58 and its emitter are held high keeping it turned off. If H. Blk is lost, then
CY99 will discharge through RZF9. CY98 is blocked by DY19 and it holds the emitter of QY58 high. This ac-
tion turns on QY58 and supplies a high through DY07 to the base of QY57. See the Mute Activation circuit ex-
plained previously.
(Continued on page 7)
PAGE 02-06
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