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This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by the use of it.
Introduction 1 Introduction This manual describes the setup and operation of the S5U13A04B00C Rev. 1.0 Evaluation Board. The board is designed as an evaluation platform for the S1D13A04 LCD/USB Companion Chip. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development.
Features 2 Features Following are some features of the S5U13A04B00C Rev. 1.0 Evaluation Board: • 121-pin PFBGA S1D13A04 Embedded Memory LCD Controller with 160K bytes of embedded SRAM. • PCI bus operation through onboard PCI bridge. • CPU/Bus interface header strips for non-PCI bus operation.
3 Installation and Configuration The S5U13A04B00C is designed to support as many platforms as possible. The S5U13A04B00C incorporates a DIP switch and five jumpers which allow both the evalu- ation board and the S1D13A04 LCD controller to be configured for a specified evaluation platform.
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CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1 SW1-8 Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host = Required settings when used with PCI Bridge FPGA Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
Installation and Configuration 3.2 Configuration Jumpers The S5U13A04B00C has five jumper blocks which configure various setting on the board. The jumper positions for each function are shown below. Table 3-2: Jumper Summary Jumper Function Position 1-2 Position 2-3 No Jumper...
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Position 1-2 sets the voltage level to 5.0V (default setting). Position 2-3 sets the voltage level to 3.3V. Note When configured for Sharp HR-TFT or Epson D-TFD panels, JP3 and JP5 must be set to position 2-3. +3.3 LCDVCC +5 LCDVCC...
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Position 1-2 GPIO0 used to control the LCD bias power supplies for STN panels. Position 2-3 GPIO0 used as the PS signal when the S1D13A04 is configured for HR-TFT panel type. HR-TFT PS GPIO0 signal Figure 3-6: Configuration Jumper (JP5) Location Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16]. These pins are not used in their corresponding host interface mode. Systems are responsible for externally connecting them to Host Interface IO V Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
Connected to WE0# of the S1D13A04 Connected to WAIT# of the S1D13A04 Connected to CS# of the S1D13A04 Connected to MR# of the S1D13A04 Connected to WE1# of the S1D13A04 Connected to +3.3V Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
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+5 volt supply Connected to RD/WR# of the S1D13A04 Connected to BS# of the S1D13A04 Connected to BUSCLK of the S1D13A04 Connected to RD# of the S1D13A04 Not connected Not connected Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
H1 setting JP4 to 2-3. When the ’Direct’ HR-TFT interface is selected, DRDY becomes a general purpose output (GPO) controllable using the ’Direct’ HR-TFT LCD Interface GPO Control bit Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
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LCD Interface Pin Mapping (REG[14h] bit 0). This GPO can be used to control the HR-TFT MOD signal if required. For further information, see the S1D13A04 Hardware Functional Specification, document number X37A-A-001-xx. Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
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GPIOs. If USB support is enabled (REG[4000h] bit 7 = 1), GPIO[7:4] are used by the USB interface. GPIO[3:0] remain available for ’Direct’ HR-TFT interface support or as GPIOs. Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
PCI Bridge FPGA to support the PCI bus. 6.2 Direct Host Bus Interface Support The S5U13A04B00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment. However, the S1D13A04 directly supports many other host bus interfaces.
+23V and +40V (I =45mA). Such a power supply (VDDH) has been provided on the S5U13A04B00C board. VDDH can be adjusted using R22 to provide an output voltage from +23V to +40V, and is enabled/disabled using the S1D13A04 general purpose signal, GPIO0 (active high).
The S1D13A04 USB controller provides a Revision 1.1 compliant USB client. The S1D13A04 acts as a USB device and connects to an upstream hub or USB host through connector J1 on the S5U13A04B00C evaluation board. Clamping diodes have been added to protect the USB bus from ESD and shorting.
Clock Synthesizer and Clock Options 7 Clock Synthesizer and Clock Options For maximum flexibility, the S5U13A04B00C implements a Cypress ICD2061A Clock Synthesizer. MCLKOUT from the clock synthesizer is connected to CLKI2 of the S1D13A04 and VCLKOUT from the clock synthesizer is connected to CLKI of the S1D13A04.
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Jumper Shunts PCI bracket with slot for USB PCI Bracket Hansen Industries Type B connector Use to Assemble PCI bracket Screw Screw, pan head, #4-40 x 1/4" onto PCB board Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board Rev. 3.1...
Sales and Technical Support 12 Sales and Technical Support For more information on Epson Display Controllers, visit the Epson Global website. https://global.epson.com/products_and_drivers/semicon/products/display_controllers/ For Sales and Technical Support, contact the Epson representative for your region. https://global.epson.com/products_and_drivers/semicon/information/support.html Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board...
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