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Technical Description
6 Technical Description
6.1 PCI Bus Support
The S1D13A04 does not have on-chip PCI bus interface support. The S1D13A04B00C
uses the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13A04B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13A04 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see "CPU
Interface" on page 12.
Note
6.3 S1D13A04 Embedded Memory
The S1D13A04 has 160K bytes of embedded SRAM. The 160K byte display buffer address
space is directly and contiguously available through the 18-bit address bus.
6.4 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide
between -14V and -24V (I
the S5U13A04B00C board. VLCD can be adjusted using potentiometer R39 to provide an
output voltage from -14V to -24V, and is enabled/disabled using the S1D13A04 general
purpose signal, GPIO0 (active high).
Note
18
All manuals and user guides at all-guides.com
The PCI Bridge FPGA must be disabled using SW1-8 in order for direct host bus inter-
face to operate properly.
out
When manually adjusting the voltage, set the potentiometer according to the panel's
specific power requirements before connecting the panel.
Seiko Epson Corporation
=45mA). Such a power supply (VLCD) has been provided on
S5U13A04B00C Rev 1.0 Evaluation Board
Rev. 3.1
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