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PCLK
PDATA
6
PALE
Figure 5. Configuration registers read operation
Parameter
Symbol
PCLK, clock
F
CLOCK
frequency
PCLK low
T
CL,min
pulse
duration
PCLK high
T
CH,min
pulse
duration
PALE setup
T
SA
time
PALE hold
T
HA
time
PDATA setup
T
SD
time
PDATA hold
T
HD
time
Rise time
T
rise
Fall time
T
fall
Note: The set-up- and hold-times refer to 50% of VDD.
Address
Read mode
5
4
3
2
1
0
Min
Max
Units
-
10
MHz
50
ns
50
ns
10
-
ns
10
-
ns
10
-
ns
10
-
ns
100
ns
100
ns
Table 2. Serial interface, timing specification
SWRS048A
R
7
6
5
Conditions
The minimum time PCLK must be low.
The minimum time PCLK must be high.
The minimum time PALE must be low before
negative edge of PCLK.
The minimum time PALE must be held low after
the positive edge of PCLK.
The minimum time data on PDATA must be ready
before the negative edge of PCLK.
The minimum time data must be held at PDATA,
after the negative edge of PCLK.
The maximum rise time for PCLK and PALE
The maximum fall time for PCLK and PALE
CC1000
Data byte
4
3
2
1
0
Page 14 of 55
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