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EVM Digital Configuration
5
EVM Digital Configuration
The EVM offers two jumpers (JP2 and JP3) to configure the EVM in either 3-wire SPI mode or 4-wire SPI
mode.
5.1
SPI 3-Wire Mode (JP2:2–3 and JP3:OPEN)
This mode is used to communicate with the MMB0 motherboard. Use the chip-select signal to bring the
ADS8339 digital output out of tri-state mode and initialize conversions. The rising edge of the chip-select
signal starts a conversion, and after the conversion time, the falling edge of the chip-select signal brings
the digital output out of tri-state mode.
5.2
SPI 4-Wire Mode (JP2:1–2 and JP3:CLOSED)
The chip-select signal is used to bring the ADS8339 digital output out of tri-state. However, conversion is
initialized from J3:17 as an independent signal. The rising edge of J3:17 (CONVST) starts a conversion,
and after the conversion time, the falling edge of the chip-select signal brings the digital output out of tri-
state.
Figure 5
shows the serial configuration for this mode.
8
ADS8339EVM-PDK
Figure 4
shows the serial configuration for this mode.
DVDD
10 k
SDI
SCLK
SDO
CS
CONVST
Figure 4. Serial 3-Wire Configuration
DVDD
10 k
SDI
CS
SCLK
SDO
CONVST
CONVST
Figure 5. Serial 4-Wire Configuration
Copyright © 2014–2015, Texas Instruments Incorporated
JP2
CS ( J2:1 or J2:7 )
2
3
JP3 (OPEN)
J2:17
JP2
1
CS ( J2:1 or J2:7 )
2
3
CONVST (J2:17)
JP3 (CLOSED)
SBAU233A – October 2014 – Revised November 2015
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