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2.2.3
Chipset
Combining the memory and I/O controller functions into a single component, the
3100 chipset includes a four-channel Enhanced Direct Memory Access (EDMA) con-
troller, offering low-latency and high throughput data transfer capability with no CPU
intervention for higher overall system performance. It also integrates I/O controller
features such as Serial ATA, PCI, UART, and USB, saving board real-estate and
power by removing the need for a separate, legacy I/O bridge chip. For demanding I/
O and networking applications, the PCIe interfaces from the chipset provide through-
put speeds of up to 4 GB/s on the x8 interface, and up to 2 GB/s on the x4 interfaces.
Refer to the following figure for the chipsets I/O interfaces.
2.2.4
Memory
The Intel 3100 provides an integrated memory controller for direct connection to one
channel of DDR2-400 registered memory devices with ECC. The memory controller
is located behind the Bus 0 as Device 0, Function 0. The DRAM Controller Error
Reporting Registers are located in Function 1 of the Device 0. The Intel 3100 mem-
ory interface supports 512 Mbit, 1 Gbit and 2 Gbit memory technologies. However, as
product options, the MIC-5602 uses 9 pieces of either 1 Gbit (128 Mb x 8) or 2 Gbit
(256 Mb x 8) SDRAM.
2.2.5
Ethernet Controller
The MIC-5602 uses one Intel 82571EB LAN controller, connected to the 3100 chipset
through a PCIe x4 interface, to provide one GbE connection (PHY mode) accessible
on the AMC front panel via a RJ-45 port and two SerDes links routed to the AMC
common options region (port 0 and port 1). However, the PHY mode and the SerDes
link on port 1 can not be accessed simultaneously (mutually exclusive). They are
switchable through a BIOS setup item.
MIC-5602 User Manual
Figure 2.1 Intel 3100 Chipset
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