Figure 14. Host Port Read Cycle Timing; Figure 15. Host Port Write Cycle Timing - Cirrus Logic CobraNet Silicon Series Hardware User Manual

HADDR[3:0]
HDATA[7:0]
HEN
t
m rw su
HR/W
HDS
HREQ
H A D D R [3 :0 ]
t
H D A T A [7 :0 ]
H E N
H R /W
H D S
H R E Q
DS651UM21
Version 2.1
t
t
m as m ah
LSP
t
m dhr
t
m dd
t
m cdr
t
m rp w

Figure 14. Host Port Read Cycle Timing

t
m as
m ah
L S P
t
m d su
t
m cdw
t
m rw su

Figure 15. Host Port Write Cycle Timing

©
Copyright 2004 Cirrus Logic, Inc.
CobraNet Hardware User's Manual
M SP
t
m dis
t
m rd
M S P
t
m dhw
t
m w p w
t
m w d
t
m rw irq l
Host Management Interface (HMI)
t
m rw hld
t
m rdtw
t
m rwirqh
t
m rw h ld
t
m w trd
25