Synchronization; Synchronization Modes; Figure 3. Audio Clock Sub-System - Cirrus Logic CobraNet Silicon Series Hardware User Manual

CobraNet Hardware User's Manual

Synchronization

5.0 Synchronization
Figure 3
circuitry allows the synchronization modes documented below to be achieved. Modes are
distinguished by different settings of the multiplexors and software elements.
VCXO
DAC
24.576 MHz
±100 PPM
MCLK_IN
MCLK_SEL
RefClkEnable
RefClkPolarity
REFCLK
BeatReceived
5.1

Synchronization Modes

Clock synchronization mode for conductor and performer roles is independently
selectable via management interface variables syncConductorClock and
syncPerformerClock. The role (conductor or performer) is determined by the network
environment including the conductor priority setting of the device and the other devices on
the network. It is possible to ensure you will never assume the conductor role by selecting
a conductor priority of zero. However, it is not reasonable to assume that by setting a high
conductor priority, you will always assume the conductor role. For more information, refer
to CobraNet Programmer's Reference Manual.
16
shows clock related circuits for the CS181xx and board design (CM-2). This
Edge
Detect

Figure 3. Audio Clock Sub-system

©
Copyright 2004 Cirrus Logic, Inc.
AClkConfig
Audio
Clock
Generator
Sample
Phase
Counter
Phase
Detector
CS181xx
Legend:
External
Hardware
Component
(CM2)
MCLK_OUT
FS1
SCK
Loop
Filter
Internal
Hardware Software
Component Component
(CS181xx)
DS651UM21
Version 2.1