Host Management Interface (Hmi); Hardware - Cirrus Logic CobraNet Silicon Series Hardware User Manual

7.0 Host Management Interface (HMI)

7.1

Hardware

The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers
are implemented. The upper two registers can be used to configure and retrieve the
status on the host port hardware. However, only the first 8 are essential for normal HMI
communications. It is therefore feasible, in most applications, to utilize only the first 3
address bits and tie the most significant bit (A3) low.
Host port hardware supports Intel, Motorola, and Motorola multiplexed bus protocols in
big-endian or little-endian modes. Standard CobraNet firmware configures the port in the
Motorola, big-endian mode.
The host port memory map is shown in
page 31 and
0
1
2
3
4
5
6
7
8
9
The message and data registers provide separate bi-directional data conduits between
the host processor and the CS181xx. A 32-bit word of data is transferred to the CS181xx
when the host writes the D message or data register after presumably previously writing
the A, B, and C registers with valid data. Data is transferred from the CS181xx following a
read of the D message or data register. Again, presumably the A, B, and C registers are
read previously.
Two additional hardware signals are associated with the host port: HACK and HREQ.
Both are outputs to the host.
HACK may be wired to an interrupt request input on the host. HACK can be made to
assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is
deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see "Messages"
below).
DS651UM21
Version 2.1
"HMI Access Code" on page
Host Address
Message A (MS)
Message B
Message C
Message D (LS)
Data A (MS)
Data B
Data C
Data D (LS)
Control
Status
Table 3. Host port memory map
©
Copyright 2004 Cirrus Logic, Inc.
CobraNet Hardware User's Manual
Host Management Interface (HMI)
Table 3. Refer also to "HMI Definitions" on
32.
Register
23