Stanford Research Systems SR865A Operation Manual page 10

4 mhz dsp lock-in amplifier
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Specifications
Sine Output
Outputs
Output Impedance
Amplitude
Amplitude Resolution
dc Offset
Offset Resolution
Output Limit
Sync
Data
Data Channels
Data Sources
Data History
Offset
Ratio
Expand
Capture Buffer
Data Streaming
Scanning
FFT
Source
Record length
Averaging
Inputs and Outputs
CH 1 Output
CH 2 Output
X and Y Outputs
BlazeX
Aux Outputs
Aux Inputs
Trigger Input
Monitor Output
HDMI
Timebase Input/Output
SR865A DSP Lock-in Amplifier
Differential or Single-ended
50 Ω source
1 nVrms to 2 Vrms (specified amplitude is differential into 50 Ω loads)
Output amplitude is halved when used single-ended
Output amplitude is doubled into a high impedance load
3 digits or 1 nV, whichever is greater
±5 V, differential or common mode
3 digits or 0.1 mV, whichever is greater
±6 V, sum of dc offset and peak amplitude
Logic level sync on rear panel (via BlazeX output)
4 data channels are displayed and graphed (green, blue, yellow, orange)
Each data channel can be assigned any of these data sources:
X, Y, R, θ, Aux In 1–4, Aux Out 1–2, X
DC Level, reference phase, f
All data sources are continuously stored at all chart display time scales.
The complete stored history of any data source can be displayed at any time.
X, Y and R may be offset up to ±999% of the sensitivity
X, and Y may be ratioed by Aux In 3; R may be ratioed by Aux In 4
X, Y and R may be expanded by ×10 or ×100
1 Mpoints internal data storage. Store (X), (X and Y), (R and θ) or (X, Y, R and θ)
at sample rates up to 1.25 MHz. This is in addition to the data histories for the
chart display.
Realtime streaming of data, either (X), (X and Y), (R and θ) or (X, Y, R and θ) at
sample rates up to 1.25 MHz over Ethernet interface
One of the following parameters may be scanned:
f
, Sine Out Amplitude, Sine Out DC Level, Aux Out 1 or 2.
int
Input ADC, demodulator output, or filter output
1024 bins
exponential rms
Proportional to X or R, ±10 V full scale thru 50 Ω
Proportional to Y or θ, ±10 V full scale thru 50 Ω
Proportional to X and Y, ±10 V full scale thru 50 Ω, rear panel
Low latency output of X, ±2.0 V full scale or
logic level reference sync output, either thru 50 Ω
4 BNC D/A outputs, ±10.5 V thru 50 Ω, 1 mV resolution
4 BNC A/D inputs, ±10.5 V, 1 mV resolution, 1 MΩ input
TTL input triggers storage into the internal capture buffer
Analog output of the signal amplifier
Video output to external monitor or TV, 640x480/60 Hz.
1 Vrms 10 MHz clock to synchronize internal reference frequency to other units
, Y
, Sine Out Amplitude, Sine Out
noise
noise
or f
int
ext

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