Dram Clock; Sdram Cycle Length; Bank Interleave; Memory Hole - Advantech PCA-6004V-00A1 Manual

3.5.1 DRAM Clock

This item allows you to control the DRAM speed. The Choice: Host
Clock, CLK-33M.

3.5.2 SDRAM Cycle Length

When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field
from the default value specified by the system designer. The Choice:
2, 3.

3.5.3 Bank Interleave

This item allows you to select the value in this field, depending on
whether the board has paged DRAMs or EDO (extended data output)
DRAMs. The Choice: EDO 50ns, EDO 60ns,Slow, Medium, Fast,
Turbo.

3.5.4 Memory Hole

In order to improve performance, certain space in memory is reserved
for ISA cards. This memory must be mapped into the memory space
below 16MB. The Choice: 15M-16M, Disabled.

3.5.5 P2C/P2P Concurrency

This item allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency. The Choice: Enabled, Disabled

3.5.6 System BIOS Cacheable

Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result. The
choice: Enabled, Disabled.

3.5.7 AGP Aperture Size

Select the size of Accelerated Graphics Port (AGP) aperture. The
Chapter 3 Award BIOS Setup 33