Pci Delay Transaction; Pci#2 Access #1 Retry; Agp Master 1 Ws Write; Memory Parity/ Ecc Check - Advantech PCA-6004V-00A1 Manual

3.5.14 PCI Delay Transaction

The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1. The choice: Enabled, Disabled

3.5.15 PCI#2 Access #1 Retry

When disabled, PCI#2 will not be disconnected until access finishes
(difault). When enabled, PCI#2 will be disconnected if max retries are
attempted without success. The choice: Enabled, Disabled

3.5.16 AGP Master 1 WS Write

When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choice: Enabled, Disabled

3.5.17 Memory Parity/ ECC Check

Enabled add a parity check to the boot-up memory test. Select
Enabled when only system DRAM contains parity. The Choice:
Enable, Disable.
3.6

Integrated Peripherals

Figure 3-5: Integrated peripherals
Chapter 3 Award BIOS Setup 35