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Chapter 1 Explanation of Functions
1.1 Principles of Waveform Generation
IM 707281-01E
The 4-CH, 100 kS/s D/A Module WE7281/WE7282 has DC, AG, and FG waveform generation
modes. Of the three modes, the operation principles of AG and FG modes are described here.
AG mode
In the AG mode, waveform data previously written to the waveform memory are read
according to the specified sampling interval and output sequentially (digital synthesis).
As shown in the figure below, the address counter operates based on the clock, which
has a frequency that is the inverse of the sampling interval, and provides addresses to
the waveform memory. Data obtained from the waveform memory of the specified
address are converted to an analog signal by the D/A converter and high frequency
components are removed by the LPF. The data processor inside the module carries out
the address counter operation, the reading of waveform data from the waveform
memory, and the configuration of the waveform output D/A.
Address
Waveform
counter
memory
Clock
FG mode
In the FG mode, waveform is generated using DDS (Direct Digital Synthesis). As shown in
the figure below, DDS is composed of a reference clock signal generator, a phase
computing unit, a waveform memory containing one cycle of waveform data, a D/A
converter, a LPF, and other components. Because the waveform memory only stores the
data for one-cycle of the waveform, the address values correspond to the phase angles of
the waveform.
Phase computing unit
N
Adder
Latch
Reference clock
If N is one input to the adder and the other input is 0, the adder outputs N. The latching
circuit outputs N in sync with the standard clock. This value, N, will be the first address
of the waveform memory. Next, the N that is output from the latching circuit is input to
the adder which then outputs 2N. The latching circuit outputs 2N in sync with the next
clock cycle. The result is continuously added and the phase computing unit outputs 3N,
4N, and so on, for every clock cycle. These values, N, 2N, 3N, ... become the waveform
memory addresses. The data at the specified address is converted to an analog signal
through the D/A converter, and high frequency components are removed with the LPF.
In this DDS method, If the value N is applied to the input of the phase computing unit
such that the specified address is three greater than the previous address, the output
frequency will be increased by a factor of three if the clock frequency stays the same.
Thus, the output frequency of the waveform can be adjusted by changing the value of N.
Also, by changing the data in the waveform memory, the circuit can output other wave-
forms such as triangular and pulse waveforms that are provided by the module as well
as arbitrary waveforms that are loaded externally.
The data processor inside the module carries out the phase computing unit operation,
the reading of waveform data from the waveform memory, and the configuration of the
waveform output D/A.
Waveform
LPF
output D/A
Waveform
LPF
output D/A
Waveform
memory
Waveform
output
Waveform
output
1-1
1
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