Power Supplies - Texas Instruments ADS7042EVM-PDK User Manual

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Finally, Figure 2-3 identifies a do-not-populate (DNP) component in U9. This ADC footprint is on the bottom of
the board and can be used to evaluate any differential ADC in a VSSOP package in
that any device in U5 is cleanly removed before soldering a device in U9.
ADS704X-5XEVM GUI to update the EEPROM when the ADC is replaced.

2.2 Power Supplies

The default state of the EVM has all power supplies derived from the USB power and delivered by the PHI
controller. The 3.3-V ADC digital supply voltage (DVDD) is provided by the PHI via pin 50 on J4 (see
2-7). The PHI also provides a regulated 5.5-V power rail that feeds into two LDOs on the EVM. These LDOs
generate a low-noise, 3.6-V (nominal) supply voltage for the amplifier (OPA_VDD) and a low-noise, 3.3-V
(nominal) analog supply voltage for the ADC (AVDD).
ADS704X-5XEVM.
EVM_REG_5V5
C4
1µF
C6
1µF
In Figure 2-4, the top LDO (U1) has an adjustable output set by resistors R31 and R32 while the bottom
LDO (U2) has an adjustable output set by resistors R33 and R34. Modify these resistor values if a different
OPA_VDD or AVDD voltage is desired. Ensure that the input, absolute, and common-mode voltage limitations
for all components are within data sheet limits when modifying the power supplies. See the LDO data sheet for
more information on how to choose resistor values for a specific output voltage.
If external power supplies are desired, remove resistors R1 and R6 in
the power-supply circuit. Connector JP4 in
AVDD, and OPA_VSS.
Figure 2-5. External Power-Supply Header on the ADS704X-5XEVM
If OPA_VSS is connected to any voltage other than AGND, remove R4 in
per the instructions in Figure
(pin 4) on the buffer amplifier in
on OPA_VSS is changed.
SBAU382 – NOVEMBER 2021
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U1
TPS79101DBVR
1 6
IN OUT
3 5
EN FB
4
BYPASS
GND
R2 C18
0 10nF
U2
TPS79101DBVR
1 6
IN OUT
3 5
EN FB
4
BYPASS
GND
R8 C21
0 10nF
Figure 2-4. Power Tree on the ADS704X-5XEVM
Figure 2-5
JP4
1
2
3
2-2. Another important consideration if OPA_VSS is modified is that the V– input
Figure 2-6 is hard-wired to AGND and is therefore unaffected when the voltage
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Section 4.6
Figure 2-4 shows the two LDO circuits used on the
R1
0
R31
C5
59.0k C7
15pF
10V
10uF
R32
30.1k
AGND
R6
0
R33
C19 R3
51.1k C20
15pF 301k
10V
10uF
R34
R5
30.1k
100k
Figure 2-4
can then be used to provide direct power to OPA_VDD,
OPA_VDD
AVDD
OPA_VSS
R4
0
AGND
Figure 2-5
ADS7042EVM-PDK, ADS7049-Q1EVM-PDK, and ADS7057EVM-PDK
Introduction to the ADS704X-5XEVM
Table 1-2. However, ensure
explains how to use the
Figure
OPA_VDD
AVDD
R7
100k
R39
AVDD/4 AVDD/2
DNP
0
R9
100k
AGND
to disconnect both LDOs from
and replace R43 and R44
Evaluation Module
7