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4 Power Supplies
The ADS8353-Q1 supports a wide range of operation on the analog supplies. The AVDD operates from 4.5 V
to 5.5 V. The DVDD operates from 1.65 V to 5.5 V, independent of the AVDD supply. The analog portion of the
ADS8353-Q1EVM operates from a 5.3-V supply (VA) generated using the TPS7A47-Q1 low-noise, low-dropout
regulator. The same supply is used to power the OPA320-Q1 front-end driver amplifiers.
The TPS7A47-Q1 regulator can be configured to generate a VA supply other than 5.3 V through programmable
pin settings. For more information, see the Detailed Description section of the TPS7A47-Q1 device
The digital portion of the ADC operates from a 3.3-V EVM_DVDD supply from the PHI.
4.1 ADC Input Driver Configuration
The ADS8353-Q1 supports modes where the ADC inputs can be configured as single-ended or pseudo-
differential. The ADS8353-Q1 EVM allows the user to configure the ADC input driver amplifier either to drive
single-ended ADC inputs or pseudo-differential ADC inputs. In the single-ended configuration, the individual
ADC AINM pins are connected to ground and a unipolar signal is applied to AINP. In the pseudo-differential
configuration, the individual ADC AINM pins are driven with a DC voltage of either V
or V
(0 V to 2 × V
range). For various analog input full-scale ranges supported by the ADS8353-Q1 in
REF
REF
either single-ended or pseudo-differential mode, see the
configurations required for the single-ended and pseudo-differential configurations.
Table 4-1. Jumper Settings for ADC Input Driver Configuration
ADC Input Type
Single-ended analog inputs
Pseudo-differential analog
inputs
4.2 ADC Voltage Reference Configuration
The ADS8353-Q1 has a low-noise, low-drift, 2.5-V internal voltage reference. By default, the ADS8353-Q1 EVM
is configured to work with the ADC internal reference voltage of 2.5 V. The same reference voltage is brought
on pin 1 of jumpers JP6 and JP7 that can be used to drive the ADC AINM pin when used in pseudo-differential
configuration (either in 0 V to V
There is also a provision for using an external voltage reference for the ADC. The external reference voltage can
be generated by populating the REF34-Q1 (U8), the two OPA320-Q1 (U9, U10) and biasing components around
U8, U9, and U10. By default, the external reference, amplifiers and biasing components around U8, U9, and U10
are not populated on the board. When using an external reference, the ADS8353-Q1 internal voltage reference
must be disabled and the device must be programmed to accept the external reference voltage on the REFIO_x
pins.
SBAU327A – JANUARY 2019 – REVISED APRIL 2023
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ADC Input Full-Scale Range
0 V to V
and 0 V to 2 × V
REF
REF
0 V to V
REF
0 V to 2 × V
REF
or 0 V to 2 × V
REF
REF
Copyright © 2023 Texas Instruments Incorporated
ADS8353-Q1
data sheet.
Default Jumper
Setting
J6, J7 = Open
JP6, JP7 = Open
J6, J7 = Open
JP6, JP7 = Open
J6, J7 = Open
JP6, JP7 = Open
analog input range).
ADS8353Q1EVM-PDK Evaluation Module
Power Supplies
data
sheet.
/ 2 (0 V to V
range)
REF
REF
Table 4-1
shows the jumper
Required Jumper Setting
Short pins J6[2-3] and J7[2-3]
Open
Short pins J6[1-2] and J7[1-2]
Short pins JP6[1-2] and JP7[1-2]
Short pins J6[1-2] and J7[1-2]
Open
7
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