ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation
This document outlines the basic steps and functions that are required to ensure the proper operation of
the Texas Instruments (TI) ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Modules (hereafter in
this document, ADS42JBxxEVM or EVM). The EVM package includes an ADS42JBxxEVM, a 5-VDC
power supply, and a mini-USB cable. This EVM is designed to be used with the TSW14J5xEVM (a
JESD204B data capture card). The ADS42JBxx EVM can also be connected to all FPGA development
platforms with an FMC connector for evaluation. The ADS42JBxxEVM includes either an ADS42JB49 (14-
bit), or ADS42JB69 (16-bit) dual-channel, 250-MSPS, or an ADS42JB46 (14-bit) dual channel, 160-MSPS
analog-to-digital converter. The EVM also includes a TI LMK04828 clock jitter cleaner to provide a low
jitter/phase noise sampling clock to the ADC. This user's guide outlines the steps to quickly evaluate the
performance of the ADS42JBxx ADC by capturing and displaying signal waveforms using the
TSW14J5xEVM and the High Speed Data Converter Pro GUI software. The EVM schematics, BOMs, and
layout files are found in the design package under the ADS42JBxxEVM product folder available on
http://www.ti.com.
spacer
spacer
...................................................................................................................
1
1.1
Overview
1.2
2
2.1
2.2
3
3.1
3.2
3.3
LMK Controls
3.4
Low Level View
1
Block Diagram of the ADS42JBxxEVM
2
EVM Hardware Setup
3
ADS42JBxx EVM GUI Setup
4
HSDC Pro Software Setup
5
ADC Data Capture, 25 MHz Sinusoid, 250 MSPS Sampling Rate
6
Top-Level Block Diagram Window of the ADS42JBxx GUI
7
8
9
10
11
12
Low Level View
SLAU467D - November 2012 - Revised February 2017
Submit Documentation Feedback
.............................................................................................................
.......................................................................................................
.............................................................................................................
...........................................................................................................
..........................................................................................................
............................................................................................
......................................................................................................
......................................................................................................
....................................................................................................
...................................................................................
.......................................................................................................
...............................................................................................
.................................................................................................
.................................................................................................
...............................................................................
........................................................................................
.............................................................................................................
Copyright © 2012-2017, Texas Instruments Incorporated
SLAU467D - November 2012 - Revised February 2017
Contents
..............................................................
List of Figures
...................................................
............................................................
........................................................................
........................................................
ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module
User's Guide
Module
2
2
3
4
4
5
9
9
10
13
17
3
5
6
7
8
9
10
13
14
15
16
17
1