Advanced Chipset Features Page - PCchips M921 Series User Manual

Advanced Chipset Features Page

This page sets some of the parameters of the mainboard
components including the memory, and the system logic.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
Advanced Chipset Features
DRAM Clock/Drive Control
AGP & P2P Bridge Control
CPU & PCI Bus Control
Memory Hole
System BIOS Cacheable
Video RAM Cacheable
Memory Parity/ECC Check
    : Move
Enter : Select
F1:General Help F59:Previous Values
DRAM This item has several sub-items: Current FSB
Clock/Drive Frequency displays front-side bus (FSB)
Control frequency; Current DRAM Frequency
displays memory (DRAM) frequency; DRAM
Clock enables you to manually set the DRAM
Clock; DRAM Timing enables the system to
automatically set the SDRAM timing by SPD
(Serial Presence Detect) when being set to
default value. SDRAM CAS Latency enables
you to select the CAS latency time in HCLKs
of 2/2 or 3/3. When enabling the Bank
Interleave, memory speed is increased;
Precharge to Active can designate the
minimum Row Precharge time of the SDRAM
devices on the module; Active to Precharge
specifies the number of clock cycles; Active to
CMD specifies the minimum required delay
between activation of different rows; DRAM
Burst LEN describes which burst lengths are
supported by the devices on the mainboard.
3: BIOS Setup Utility
[Press Enter]
Item Help
[Press Enter]
[Press Enter]
Menu Level
[Disabled]
[Enabled]
[Enabled]
[Disabled]
+/-/PU/PD:Value: F10: Save ESC: Exit
F6:Fail-Safe Defaults F7:Optimized Defaults
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