Advanced Chipset Features Page - PCchips M786 Series User Manual

Mainboard User's Manual
Video BIOS
When enabled this item copies the VGA BIOS into
system DRAM.
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C8000-CBFFF to When enabled, the ROM with the specified address
is copied into system DRAM. It will also reduce the
DC000-DFFFF
size of memory available to the system.
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Advanced Chipset Features Page

This page sets some of the parameters of the mainboard
components including the memory, and the system logic.
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
DRAM Timing By SPD
SDRAM Cycle Length
Bank Interleave
DRAM Clock
P2C/C2P Concurrency
System BIOS Cacheable
Video RAM Cacheable
Frame Buffer Size
AGP Aperture Size
OnChip USB
OnChip USB 2
USB Keyboard Support
OnChip Sound
OnChip Modem
PCI Master 0 WS Write
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
Memory Parity/ECC Check
    : Move
Enter : Select
F1:General Help
Defaults F7:Optimized Defaults
DRAM Timing By
This item allows you to enable or disable the
DRAM timing defined by the Serial Presence
SPD
Detect electrical.
SDRAM Cycle This field enables you to set the CAS latency time
in HCLKs of 2/2 or 3/3. The system board
Length
designer should have set the values in this field,
depending on the DRAM installed. Do not change
the values in this field unless you change
specifications of the installed DRAM or the
installed CPU.
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Advanced Chipset Features
Disabled
3
Disabled
Host CLK
Enabled
Enabled
Enabled
8M
64M
Enabled
Disabled
Disabled
Auto
Auto
Enabled
Enabled
Disabled
Disabled
Disabled
+/-/PU/PD:Value: F10: Save
F5:Previous Values
Item Help
Menu Level
ESC: Exit
F6:Fail-Safe