Control And Indicator Signals - Quectel EM12-G Hardware Design

PCM_SYNC 28
PCM_CLK 20
I2C_SCL 58
I2C_SDA 56
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] for details about AT+QDAI command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_CLK
PCM_SYNC
PCM_OUT
Module
Figure 19: Reference Circuit of PCM Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. EM12-G works as a master device pertaining to I2C interface.

3.10. Control and Indicator Signals

The following table shows the pin definition of control and indicator signals.
EM12-G_Hardware_Design
PCM data frame
IO
synchronization signal
IO PCM data bit clock
DO I2C serial clock
IO I2C serial data
PCM_IN
I2C_SCL
I2C_SDA
1.8V
1.8V power domain.
1.8V power domain.
In master mode, it is an output
signal. In slave mode, it is an
input signal.
If unused, keep it open.
Used for external codec.
Require an external pull-up to
1.8V.
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
LTE-A Module Series
EM12-G Hardware Design
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