Rabbit RabbitCore RCM3100 User Manual page 104

Distributor of Digi International: Excellent Integrated System Limited
Datasheet of 101-0533 - KIT DEV RABBIT3000/RCM3100
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The Quadrature Decoder generates an interrupt when the counter increments from 0x00 to
0x01 or when the counter decrements from 0x00 to 0xFF. Note that the status bits in the
QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared
by reading the QDCSR.
Table E-5. Quadrature Decoder Registers
Register Name
Quad Decode Control/Status
Register
Bit
7
(rd-only)
6
(rd-only)
5
4
(wr-only)
3
(rd-only)
2
(rd-only)
1
Bit
0
(wr-only)
User's Manual
Mnemonic
QDCSR 10010000 (0x90)
Value
0 Quadrature Decoder 2 did not increment from 0xFF.
Quadrature Decoder 2 incremented from 0xFF to
1
0x00. This bit is cleared by a read of this register.
0 Quadrature Decoder 2 did not decrement from 0x00.
Quadrature Decoder 2 decremented from 0x00 to
1
0xFF. This bit is cleared by a read of this register
0 This bit always reads as zero.
0 No effect on the Quadrature Decoder 2.
Reset Quadrature Decoder 2 to 0x00, without
1
causing an interrupt.
0 Quadrature Decoder 1 did not increment from 0xFF.
Quadrature Decoder 1 incremented from 0xFF to
1
0x00. This bit is cleared by a read of this register.
0 Quadrature Decoder 1 did not decrement from 0x00.
Quadrature Decoder 1 decremented from 0x00 to
1
0xFF. This bit is cleared by a read of this register.
0 This bit always reads as zero.
Value
0 No effect on the Quadrature Decoder 1.
Reset Quadrature Decoder 1 to 0x00, without
1
causing an interrupt.
Address
Description
Description
97