Digital Di/O Definition; Configuration Sequence - Advantech ITA-5831 Series User Manual

Note!
Download the specifications for programming the NXP Semiconductors'
PCA9554 GPIO IC from the NXP website.
https://www.nxp.com/docs/en/data-sheet/
PCA9554_9554A.pdf?fsrch=1&sr=1&pageNum=1
6.1

Digital DI/O Definition

See Section 2.3.3.
6.2

Configuration Sequence

ITA-5831's GPIO is realized through the PCA9554 GPIO IC connected to ICH
SMBUS. Therefore, the GPIO IC is configured and accessed through I/O space via
the ICH SMBUS controller..
Table 6.1: ICH SMBUS I/O Space
SMB_BASE+
Offset
00h
02h
03h
04h
05h
06h
ITA-5831 User Manual
Mnemonic Register Name
HST_STS Host status
HST_CNT Host control
HST_CMD Host command
XMIT_SLVA Transmit slave address 00h
HST_D0 Host data 0
HST_D1 Host data 1
Default Type
00h R/WC,RO, R/WC (special)
00h R/W,W O
00h R/W
R/W
00h R/W
00h R/W
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