Pca9554 Register 0 - Input Port Register; Pca9554 Register 1 - Output Port Register - Advantech ITA-5831 Series User Manual

6.2.2 PCA9554 Register 0 – Input Port Register
This register is read-only and reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writing to the
register has no effect. The default "X" is determined by the externally applied logic
level, which is normal "1" when no external signal is applied because of the internal
pull-up resistors.
Table 6.4: Register 0 Bit Description
Bit Symbol
7 I7
6 I6
5 I5
4 I4
3 I3
2 I2
1 I1
0 I0
If one GPIO pin is set to input, the input value can be read from the bit that corre-
sponds to Register 0.
6.2.3 PCA9554 Register 1 – Output Port Register
This register reflects the outgoing logic levels of the pins defined as outputs by Reg-
isters 3. Bit values in this register have no effect on pins defined as inputs. Reads
from this register return the value that is in the flip-flop controlling the output selec-
tion, not the actual pin value.
Table 6.5: Register 1 Bit Description
Bit Symbol
7 O7
6 O6
5 O5
4 O4
3 O3
2 O2
1 O1
0 O0
If one GPIO pin is set to output, the input value can be read from the bit that corre-
sponds to Register 1.
ITA-5831 User Manual
Access Value Description
Read only X Determined by externally applying logic level
Read only X
Read only X
Read only X
Read only X
Read only X
Read only X
Read only X
Access Value
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
R 1*
66
Description
Determined by externally applying logic level