Pca9554 Register 2 - Polarity Inversion Register; Pca9554 Register 3 - Configuration Register - Advantech ITA-5831 Series User Manual

6.2.4 PCA9554 Register 2 – Polarity Inversion Register
This register allows users to invert the polarity of the input port register data. If a bit in
this register is set (write with "1"), the corresponding input port data is inverted. If a bit
in this register is cleared (write with "0"), the input port data polarity is retained.
Table 6.6: Register 2 Bit Description
Bit Symbol Access
7 N7
6 N6
5 N5
4 N4
3 N3
2 N2
1 N1
0 N0
If one GPIO pin is set to input, you can control the polarity of input pin from the bit
that corresponds to Register 2.
6.2.5 PCA9554 Register 3 – Configuration Register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with a high-impedance output driver. If
a bit in this register is cleared, the corresponding port pin is enabled as an output.
Upon reset, the I/Os are configured as inputs with a weak pull-up to VDD.
Table 6.7: Register 2 Bit Description
Bit Symbol Access
7 C7
6 C6
5 C5
4 C4
3 C3
2 C2
1 C1
0 C0
Register 3 is used to set each GPIO as input or output:
If the bit is "0", the corresponding GPIO pin is set as output.
If the bit is "1", the corresponding GPIO pin is set as input.
Value Description
R/W 0* Invert polarity of input port register data
R/W 0*
R/W 0* 0= Input port register data retained (default)
R/W 0*
R/W 0* 1= Input port register data inverted
R/W 0*
R/W 0*
R/W 0*
Value Description
R/W 1* Configures the direction of the I/O pins
R/W 1*
R/W 1* 0= Corresponding port pin is enabled as an output
R/W 1*
1= Corresponding port pin is enabled as an input
R/W 1*
(default)
R/W 1*
R/W 1*
R/W 1*
67 ITA-5831 User Manual