Ita-3630 Digital Dio Definition; Configuration Sequence - Advantech ITA-3630 Series User Manual

Please carefully read and study the below screenshots and source codes in blue.
Please download specification of NXP Semiconductors PCA955 for programming.
6.1

ITA-3630 Digital DIO Definition

See Section 2.3.6.
6.2

Configuration Sequence

ITA-3630's GPIO is realized through PCA9554 GPIO IC connected to ICH SMBUS.
Therefore, the configuration and access to GPIO IC is completed by IO Space
accessing to ICH SMBUS controller.
Below is the diagram of ICH SMBUS IO Space:
SMB_BASE + Offset
00h
02h
03h
04h
05h
06h
For ITA-3630, IO address of the above SMB_BASE is 0xF040.
The detailed SMBUS IO control access code, please refer to Chapter 3.
The corresponding SMBUS slave address of PCA9554 of GPIO 00 - GPIO 07 on
ITA-3630 is 0x40 (8bit address):
GPIO 00 – GPIO 07: PCA9554 0x40 (IO0 – IO7)
ITA-3630 User Manual
Mnemonic REgister Name
HST_STS Host Status
HST_CNT Host Control
HST_CMD Host Command
Transmit Slave
XMIT_SLVA
Address
HST_D0 Host Data 0
HST_D1 Host Data 1
50
Default Type
R/WC, RO,
00h
R/WC (special)
00h R/W, WO
00h R/W
00h R/W
00h R/W
00h R/W