Ethernet - Cypress CYW943907AEVAL1F User Manual

90% of their final values. To ensure proper bootup, the RC delay circuit for HIB_REG_ON_IN is essential as shown in
4-4.

4.4 Ethernet

The Ethernet MAC Controller in CYW43907 interfaces with an external PHY chip, BCM5241, using the Media Independent
Interface (MII) as shown in
Media Independent
10 Mbps and 100 Mbps.
Sl.No.
1
2
3
4
5
CYW943907AEVAL1F Evaluation Kit User Guide, Doc. No. 002-18703 Rev. *B
Figure 4-3. Reset Circuit Diagram
Figure 4-4. HIB_REG_ON_IN RC Delay Circuit
Figure 4-5. The same signals are also listed in
Interface (RMII). The
Table 4-4. CYW43907 EMAC to PHY Chip Connection
CYW43907 Pin Name
RMII_G_RXC
RMII_G_COL
RMII_G_CRS
RMII_G_TXC
RMII_G_TXD0
Table
controller can
Net Name in Schematic
MII_RXC
MII_COL
MII_CRS
MII_TXC_RMII_REF_CLK
MII_TXD0
4-4. CYW43907 also supports Reduced
transmit and receive
BCM5241 Pin Name
RXC
COL/ENERGYDET
CRS/STANDBY
TXC
TXD0
Hardware
Figure
data at
30