Toshiba TXZ+ TMPM4K Series Reference Manual
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Toshiba TXZ+ TMPM4K Series Reference Manual

Toshiba TXZ+ TMPM4K Series Reference Manual

32-bit risc microcontroller
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TXZ+ Family

TMPM4K Group (1)

Clock Control and Operating Mode
32-bit RISC Microcontroller
TXZ+ Family
TMPM4K Group (1)
Reference Manual
Clock Control and Operating Mode
(CG-M4K(1)-E)
Revision 1.0
2024-07
© 2023-2024
1 / 63
2024-07-22
Toshiba Electronic Devices & Storage Corporation
Rev. 1.0

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  • Page 1: Tmpm4K Group

    TMPM4K Group (1) Clock Control and Operating Mode 32-bit RISC Microcontroller TXZ+ Family TMPM4K Group (1) Reference Manual Clock Control and Operating Mode (CG-M4K(1)-E) Revision 1.0 2024-07 © 2023-2024 1 / 63 2024-07-22 Toshiba Electronic Devices & Storage Corporation Rev. 1.0...

  • Page 2: Table Of Contents

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Contents Preface ................................. 6 Related Documents ..............................6 Conventions ................................7 Terms and Abbreviations ............................9 Clock Control and Operating Mode ......................10 1.1. Outlines ................................10 1.2. Clock Control ..............................11 1.2.1.
  • Page 3 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.2. [CGOSCCR] (Oscillation control register) ........................31 1.4.2.3. [CGSYSCR] (System clock control register) ........................32 1.4.2.4. [CGSTBYCR] (Standby control register) ........................33 1.4.2.5. [CGSCOCR] (SCOUT output control register) ....................... 33 1.4.2.6.
  • Page 4 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.6.1. Reset Factors and Initialized Range of Circuits ......................61 Revision History ............................62 RESTRICTIONS ON PRODUCT USE ....................... 63 4 / 63 2024-07-22 Rev. 1.0...
  • Page 5 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode List of Figures Figure 1.1 Clock System Diagram ......................12 Figure 1.2 Mode State Transition ......................25 Figure 1.3 NORMAL Mode → STOP1 Mode → NORMAL Mode Transition ..........29 Figure 2.1 TMPM4KxFYB ..........................

  • Page 6: Preface

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Preface Related Documents Document name ® ® documentation set for the Arm Cortex Exception Oscillation Frequency Detector Voltage Detection Circuit Clock Selective Watchdog Timer Flash Memory Datasheet 6 / 63 2024-07-22 Rev.

  • Page 7: Conventions

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the "0b"...
  • Page 8 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.

  • Page 9: Terms And Abbreviations

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to Digital Converter A-ENC32 Advanced Encoder input Circuit (32-bit) A-PMD Advanced Programmable Motor Control Circuit Clock Control and Operating mode Cyclic Redundancy Check D-Bus DCode memory interface...

  • Page 10: Clock Control And Operating Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1. Clock Control and Operating Mode 1.1. Outlines The clock/mode control block can select a clock gear and prescaler clock and set the warming up of oscillator and so on. Furthermore, this product has NORMAL mode and a low-power consumption mode as the operating mode in order to reduce power consumption by operating mode transition depending on the situation.

  • Page 11: Clock Control

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2. Clock Control 1.2.1. Clock Types A list of clocks is shown below. EHCLKIN: The high-speed clock input from the external fosc: A clock generated in the internal oscillation circuit or input from the X1 and X2 pins after being selected by [CGOSCCR]<OSCSEL>...

  • Page 12: Clock System Diagram

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.3. Clock System Diagram The figure below shows a clock system diagram. TPIU [CGWUPHCR]<WUON> [CGSPCLKEN] [CGWUPHCR]<WUPT[15:4]> <ADCKEN> High-speed ADCLK warm-up timer [CGWUPHCR] <WUCLK> [CGOSCCR]<IHOSC1EN> Internal PLL for fsys IHOSC1 high-speed [CGFCEN] oscillator 1 PLL0...

  • Page 13: Warming-Up Function

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.4. Warming-up Function A warming-up function starts the warming-up timer for high-speed oscillation automatically to secure the oscillation stable time when the STOP1 mode is released. It is also available as a count-up timer which uses the warming-up timer for high-speed oscillation to secure the stability of an external oscillator or an internal oscillator.

  • Page 14: Directions For Use Of Warming-Up Timer

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.4.2. Directions for Use of Warming-up Timer The directions for use of a warming-up timer are explained. (1) Selection of a clock The warming-up timer is used for a high-speed oscillation, the clock classification (internal oscillation or external oscillation) counted with a warming-up timer is selected by [CGWUPHCR]<WUCLK>.

  • Page 15: Formula And Example Of Setting Value For Pll Multiplication Value

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.5.2. Formula and Example of Setting Value for PLL Multiplication Value The details of the items of [CGPLL0SEL]<PLL0SET[23:0]> which set up a PLL multiplication value are shown below. Table 1.1 Details of Setting Value to [CGPLL0SEL]<PLL0SET[23:0]> The items of PLL0SET Function Correction...

  • Page 16: Change Of Pll Multiplication Value Under Operating

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Table 1.2 PLL Correction (Example) <PLL0SET[23:17]> fosc (MHz) (a decimal, an integral value) 6.00 8.00 10.00 12.00 24.00 The PLL correction value can be calculated by following formula. When fosc is 6.0 MHz, the correction value if 6 / 0.45 = 13.33 → 14 ;...

  • Page 17: Procedures Of Switching Starting And Stopping Pll Operation

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.5.4. Procedures of Switching Starting and Stopping PLL Operation (1) fc setting (PLL operation stopped → PLL operation started) The example of switching procedure from the state of PLL operation stopped to the state of PLL operation started is as follows for the fc.

  • Page 18: System Clock

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.6. System Clock An internal high speed oscillation clock and external high speed oscillation clock (connected oscillator or clock input) can be used as a source of system clock. Dividing is possible for a system clock at [CGSYSCR]<GEAR[2:0]> (clock gear). Although a setup can be changed during operation, after register writing before a clock actually changes, a maximum of 16-clock time is required of fc.

  • Page 19: Procedure Of Switching Oscillator For System Clock

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.6.1. Procedure of Switching Oscillator for System Clock (1) fosc setting (Internal oscillator → External oscillator) The example of switching procedure from the internal high-speed oscillator 1 (IHOSC1) to the external high- speed oscillator (EHOSC) is shown below.
  • Page 20 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode (3) fosc setting (External oscillator or External clock input → Internal oscillator) The example of switching procedure from the external high-speed oscillator (EHOSC) or external clock input (EHCLKIN) to the external clock input (EHCLKIN) is shown below. <<...

  • Page 21: Clock Supply Setting Function

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.2.7. Clock Supply Setting Function TMPM4K Group (1) has the clock supply supply/stop function for the peripheral circuits. To reduce the power consumption, it can stop supplying the clock to the peripheral functions that are not used. Except some peripheral functions, clocks of the peripheral functions are not supplied after releasing reset.

  • Page 22: Operating Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3. Operating Mode TMPM4K Group (1) has NORMAL mode and low-power consumption modes (IDLE and STOP1) as the operating mode. The power consumption can be reduced by changing operating mode according to directions for use.

  • Page 23: Transition To And Return From Low-Power Consumption Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.1.2. Transition to and Return from Low-power Consumption Mode In order to transit to each low-power consumption mode, the IDLE or STOP1 mode is selected by the standby control register [CGSTBYCR]<STBY[1:0]>, and a WFI (Wait For Interrupt) command is executed. When the transition to the low-power consumption mode has been performed by WFI instruction, the returning from the low-power consumption mode can be performed by the reset or the interrupt generation.

  • Page 24: Peripheral Function State In Low-Power Consumption Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.1.4. Peripheral Function State in Low-power Consumption Mode The following Table 1.7 shows the operating status of the peripheral functions (block) in each operating mode. In addition, after releasing reset, the clock supply status of the peripheral functions except some peripheral functions is not supplied.

  • Page 25: Mode State Transition

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.2. Mode State Transition Reset After reset, the high-speed oscillator1 (IHOSC1) oscillates. (Note2) Interrupt NORMAL STOP1 Mode Mode (CPU stops except some peripheral functions) Instruction (Note1) Instruction Interrupt IDLE Mode (CPU stops) (Operating peripheral function can be selected)

  • Page 26: Stop1 Mode Transition Flow

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.2.2. STOP1 Mode Transition Flow Perform the following procedure when transiting to STOP1 mode. Because the STOP1 mode is released by an interrupt, set the interrupt source setting before transiting to STOP1 mode.

  • Page 27: Return From Low-Power Consumption Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.3. Return from Low-power Consumption Mode 1.3.3.1. Release Source of Low-power Consumption Mode The interrupt, Non-maskable interrupt, and reset can perform return from a low-power consumption mode. The source which can be used to release the low-power consumption mode is depending on the low-power consumption mode.

  • Page 28: Warming-Up When Releasing Low-Power Consumption Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode ● Released by an interrupt request When the interrupt request releases the low-power consumption mode, it is necessary to prepare so that interrupt request may be detected by the CPU. It is necessary that the interrupt request used for releasing STOP1 may be detected by the CPU and INTIF.

  • Page 29: Clock Operation When Operating Mode Transition

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.3.4. Clock Operation when Operating Mode Transition The clock operation is shown below when operating mode transition. 1.3.4.1. NORMAL Mode → IDLE Mode → NORMAL Mode Transition The CPU stops in the IDLE mode. The clock supply to peripheral functions keeps a setting state. Enable or disable the peripheral by the register of each peripheral function and/or a clock supply setting function, etc.

  • Page 30: Explanation Of Register

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4. Explanation of Register 1.4.1. Register list The registers related to CG and its addresses are shown below. Peripheral function Channel/Unit Base address Clock Control and Operating Mode 0x400F3000 Register name Address (Base+) CG write protection register [CGPROTECT]...

  • Page 31: Detail Of Register

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2. Detail of Register 1.4.2.1. [CGPROTECT] (CG write protection register) Bit symbol After reset Type Function 31:8 Read as "0". Control write-protection for the CG register (all registers included except this register) PROTECT[7:0] 0xC1 0xC1: CG Registers are write-enabled.

  • Page 32: Cgsyscr] (System Clock Control Register)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.3. [CGSYSCR] (System clock control register) Bit symbol After reset Type Functions 31:28 Read as "0". Prescaler clock (ΦT0) selection status 0000: fc 0100: fc/16 1000: fc/256 27:24 PRCKST[3:0] 0000 0001: fc/2 0101: fc/32 1001: fc/512...

  • Page 33: Cgstbycr] (Standby Control Register)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.4. [CGSTBYCR] (Standby control register) Bit symbol After reset Type Function 31:2 Read as "0". Select a low-power consumption mode. 00: IDLE STBY[1:0] 01: STOP1 10: Reserved 11: Reserved 1.4.2.5. [CGSCOCR] (SCOUT output control register) Bit symbol After reset Type...

  • Page 34: Cgpll0Sel] (Pll Selection Register For Fsys)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.6. [CGPLL0SEL] (PLL selection register for fsys) Bit symbol After reset Type Function PLL0 multiplication setting 31:8 PLL0SET[23:0] 0x000000 About a multiplication setting, refer to "1.2.5.2. Formula and Example of Setting Value for PLL Multiplication Value". Read as "0".

  • Page 35: Cgfsysena] (Supply Stop Register A For Fsys)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.8. [CGFSYSENA] (Supply stop register A for fsys) Bit symbol After reset Type Functions IPENA31 Read as "0". Enables the clock of T32A ch5 IPENA30 0: Clock stop 1: Clock supply Enables the clock of T32A ch4 IPENA29 0: Clock stop...
  • Page 36 TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Bit symbol After reset Type Functions Enables the clock of PORT H IPENA07 0: Clock stop 1: Clock supply Enables the clock of PORT G IPENA06 0: Clock stop 1: Clock supply Enables the clock of PORT F IPENA05 0: Clock stop...

  • Page 37: Cgfsysenb] (Supply Stop Register B For Fsys)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.9. [CGFSYSENB] (Supply stop register B for fsys) Bit symbol After reset Type Functions Enables the clock of SIWDT ch0 IPENB31 0: Clock stop 1: Clock supply Enables the clock of NBDIF IPENB30 0: Clock stop 1: Clock supply...

  • Page 38: Cgfcen] (Supply Stop Register For Fc)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode Bit symbol After reset Type Functions Enables the clock of OPAMP IPENB02 0: Clock stop 1: Clock supply Enables the clock of ADC unit B IPENB01 0: Clock stop 1: Clock supply Enables the clock of ADC unit A IPENB00 0: Clock stop...

  • Page 39: Cgspclken] (Clock Supply Stop Register For Adc And Debugging Circuit)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.4.2.11. [CGSPCLKEN] (Clock supply stop register for ADC and debugging circuit) Bit symbol After reset Type Function 31:18 Read as "0". Enable the clock for ADC Unit B (Note2) ADCKEN1 0: Clock stop 1: Clock supply Enable the clock for ADC Unit A (Note2)

  • Page 40: Information For Each Product

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.5. Information for Each Product The information about [CGFSYSENA] and [CGFSYSENB] which are different according to each product is shown below. 1.5.1. [CGFSYSENA] Table 1.10 [CGFSYSENA] Corresponding to Each Product Channel No.

  • Page 41: Cgfsysenb]

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 1.5.2. [CGFSYSENB] Table 1.11 [CGFSYSENB] Corresponding to Each Product Channel No. /unit name Bit symbol Destination M4K4 M4K2 M4K1 Input/output port name ✓ ✓ ✓ IPENB31 SIWDT ✓ IPENB30 NBDIF IPENB29 - (Note 2) IPENB28...

  • Page 42: Memory Map

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2. Memory Map 2.1. Outlines The memory maps for TMPM4K Group (1) are based on the Arm Cortex-M4 (with FPU) processor core memory map. The built-in ROM, built-in RAM and special function registers (SFR) of TMPM4K Group (1) are mapped to the Code, SRAM and peripheral regions of the Cortex-M4 (with FPU) respectively.

  • Page 43: Tmpm4Kxfyb

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.1.1. TMPM4KxFYB - Code Flash 256KB - RAM 18KB - Products TMPM4K4FYBUG, TMPM4K2FYBDUG, TMPM4K1FYBUG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault Fault 0x5E040000 0x5E040000 Code Flash...

  • Page 44: Tmpm4Kxfwb

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.1.2. TMPM4KxFWB - Code Flash 128KB - RAM 18KB - Products TMPM4K4FWBUG, TMPM4K2FWBDUG, TMPM4K1FWBUG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault Fault 0x5E040000 0x5E040000 Reserved...

  • Page 45: Bus Matrix

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.2. Bus Matrix TMPM4K Group (1) contains three bus masters such as a CPU core, DMA controller and NBDIF. Bus masters connect to slave ports (S0 to S4) of Bus Matrix. In the bus matrix, master ports (M0 to M12) connect to peripheral functions via connections described as (○) or (●) in the following figure.

  • Page 46: Configuration

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.2.1. Configuration 2.2.1.1. Single Chip Mode Cortex-M4 with FPU DMAC NBDIF Code Flash RAM0 IA(INT-IF) RAM1 RAM2 Boot ROM TSPI EI2C OPAMP UART Note T32A DMAC(SFR) IB(INT-IF) SIWDT IMN(INT-IF) TRGSEL PORT A-PMD ADCCMP...

  • Page 47: Single Boot Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.2.1.2. Single Boot Mode Cortex-M4 with FPU DMAC NBDIF Code Flash RAM0 IA(INT-IF) RAM1 RAM2 Boot ROM TSPI EI2C OPAMP UART T32A Note DMAC(SFR) IB(INT-IF) SIWDT IMN(INT-IF) TRGSEL PORT A-PMD ADCCMP A-ENC32 RAMP...

  • Page 48: Connection Table

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.2.2. Connection Table 2.2.2.1. Connection of Memory, etc. (1) TMPM4KxFYB ● Single Chip Mode Table 2.1 Single Chip Mode Master Core Core Core Start address Slave DMAC NBDIF S-Bus D-Bus I-Bus ✓...

  • Page 49: Table 2.3 Single Chip Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode (2) TMPM4KxFWB ● Single Chip Mode Table 2.3 Single Chip Mode Master Core Core Core Start address Slave DMAC NBDIF S-Bus D-Bus I-Bus ✓ Fault Fault Fault 0x00000000 Code Flash ✓...

  • Page 50: Connection Of Peripheral Functions

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 2.2.2.2. Connection of Peripheral Functions Table 2.5 Connection of Peripheral Functions Master Start Core Core Core Slave DMAC NBDIF address S-Bus D-Bus I-Bus 0x40000000 Fault Fault Fault Fault ✓ ✓ 0x4003E000 IA (INTIF) Fault...

  • Page 51: Reset And Power Supply Control

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3. Reset and Power Supply Control 3.1. Outlines Function classification Function Operation description Reset which occurs at the time of a power supply turning Power-on Reset on or turning off Reset which occurs when the voltage of power supply is LVD reset Cold reset...

  • Page 52: Reset By Power-On Reset Circuit (Without Using Reset_N Pin)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.1.1. Reset by Power-on Reset Circuit (without Using RESET_N pin) After a supply voltage exceeds the release voltage of a power-on reset circuit (POR), the internal reset is released after "Internal initialization time" is elapsed. Increase a supply voltage to an operating voltage range before "Internal initialization time"...

  • Page 53: Reset By Reset_N Pin

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.1.2. Reset by RESET_N Pin When the power supply is turned on, the timing of reset release by using RESET_N pin can be controlled. After a supply voltage exceeds the release voltage of a power-on reset circuit and even after "Internal initialization time"...

  • Page 54: Figure 3.3 Reset By Reset_N Pin (2)

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode In case of RESET_N pin input change from "Low" to "High" before "Internal initialization time" elapses, internal reset signal is released after "Internal initialization time" elapses. Goes up a supply voltage within an operating voltage range before "Internal initialization time"...

  • Page 55: Continuation Of Reset By Lvd

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.1.3. Continuation of Reset by LVD When the power supply voltage has not exceeded the LVD release voltage even after "Internal initialization time" elapsed, LVD generates the reset signal and keeps the reset state. After the power supply voltage exceeds the LVD release voltage and "LVD detection release time"...

  • Page 56: Warm Reset

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.2. Warm Reset 3.2.2.1. Warm Reset by RESET_N Pin When resetting with the RESET_N pin, set the RESET_N pin to "Low" for 17.2 µs or more while the power supply voltage is within the operating range. When the "Low"...

  • Page 57: Starting Single Boot Mode

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.3. Starting Single Boot Mode Refer to the reference manual "Flash Memory" for details of "Single Boot Mode". 3.2.3.1. Starting Single Boot Mode by RESET_N Pin When BOOT_N pin is input “Low”, if reset is released by RESET_N pin (the RESET_N pin is changed from "Low"...

  • Page 58: Starting Single Boot Mode When Power Supply Voltage Is Stable

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.3.2. Starting Single Boot Mode when Power Supply Voltage is Stable When a power supply voltage is stable within an operating voltage range, input "Low" to the RESET_N pin "Internal initialization time" or longer to reset while the BOOT_N pin is input “Low”. And release reset (the RESET_N pin is changed from "Low"...

  • Page 59: Power-On Reset Circuit

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.4. Power-on Reset Circuit The power-on reset circuit (POR) generates a reset signal when the power supply is turned on or turned off. Note: The power-on reset circuit may not operate correctly due to the fluctuation of the power supply. Equipment should be designed with full consideration of the electrical characteristics.

  • Page 60: Turning Off And Re-Turning On Of Power Supply

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.5. Turning Off and Re-turning On of Power Supply When the power supply is turned off, the power supply voltage must be down gentler gradient than Max value of "Power gradient (V )"...

  • Page 61: Table 3.1 Reset Factors And Initialized Range Of Circuits

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 3.2.6.1. Reset Factors and Initialized Range of Circuits The reset factors and initialized range of circuits are shown in Table 3.1. Table 3.1 Reset Factors and Initialized Range of Circuits Reset factors Cold Warm reset...

  • Page 62: Table 4.1 Revision History

    TXZ+ Family TMPM4K Group (1) Clock Control and Operating Mode 4. Revision History Table 4.1 Revision History Revision Date Description 2024-07-22 - First release 62 / 63 2024-07-22 Rev. 1.0...
  • Page 63 Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"...

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