Toshiba TXZ+ TMPM4K Series Reference Manual
32-bit risc microcontroller
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Summary of Contents for Toshiba TXZ+ TMPM4K Series
- Page 1 TXZ+ Family TMPM4K Group(1) Input/Output Ports 32-bit RISC Microcontroller TXZ+ Family TMPM4K Group(1) Reference Manual Input/Output Ports (PORT-M4K(1)) Revision 1.0 2024-07 1 / 40 © 2023-2024 2024-07-22 Toshiba Electronic Devices & Storage Corporation Rev. 1.0...
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Page 2: Table Of Contents
TXZ+ Family TMPM4K Group(1) Input/Output Ports Contents Preface ................................. 4 Related document ..............................4 Conventions ................................5 Terms and Abbreviations ............................7 Outlines ................................. 8 Description of Operation ..........................8 2.1. Clock Supply ..............................8 Signal Connection List ..........................9 Registers .............................. - Page 3 TXZ+ Family TMPM4K Group(1) Input/Output Ports List of Figures Figure 5.1 Port Type FTU1a ........................30 Figure 5.2 Port Type FTU2a ........................31 Figure 5.3 Port Type FTU2c ........................32 Figure 5.4 Port Type FTU3a ........................33 Figure 5.5 Port Type FTU4a ........................34 Figure 5.6 Port Type FTU5a ........................
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Page 4: Preface
TXZ+ Family TMPM4K Group(1) Input/Output Ports Preface Related Document Document name Product Information Clock Control and Operation Mode Exception Flash Memory C Interface C Interface Version A Serial Peripheral Interface 12-bit Analog to Digital Convertor 32-bit Timer Event Counter Asynchronous Serial Communication Circuit Advanced Programmable Motor Control Circuit Advanced Encoder Input Circuit (32-bit) Debug Interface... -
Page 5: Conventions
TXZ+ Family TMPM4K Group(1) Input/Output Ports Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the "0b" when the number of bits can be distinctly understood from a sentence. - Page 6 TXZ+ Family TMPM4K Group(1) Input/Output Ports All other company names, product names, and service names mentioned herein may be trademarks of their respective companies. 6 / 40 2024-07-22 Rev. 1.0...
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Page 7: Terms And Abbreviations
TXZ+ Family TMPM4K Group(1) Input/Output Ports Terms and Abbreviations Some of abbreviations used in this document are as follows: EI2C C Interface Version A Inter-Integrated Circuit JTAG Joint Test Action Group NBDIF Non- break Debug Interface Serial Wire 7 / 40 2024-07-22 Rev. -
Page 8: Outlines
TXZ+ Family TMPM4K Group(1) Input/Output Ports 1. Outlines It is described about the register and setting of port. A list of the functions is indicated below. Function Function Description classification Programmable pull-up and Programmable pull-down can be Ports selected. Open-drain output can be selected. Clock Output System clock output is possible. -
Page 9: Signal Connection List
TXZ+ Family TMPM4K Group(1) Input/Output Ports 3. Signal Connection List This table is sorted the function pins by the signal name of the block diagram (signal table) which is described each Reference Manual. Register setting of the peripherals function is explained in the port order, so please use for a reverse lookup of port name. -
Page 10: Table 3.2 Signal Connection List (2/5)
TXZ+ Family TMPM4K Group(1) Input/Output Ports Table 3.2 Signal Connection List (2/5) Function pin Port M4K4 M4K2 M4K1 Related reference manual name name (LQFP64) (LQFP48) (LQFP44) T32A00INA0 T32A00OUTA T32A00INC0 T32A00OUTC T32A01INA0 T32A01INA1 T32A01OUTA T32A01INB0 T32A01OUTB T32A01INC0 T32A01INC1 T32A01OUTC T32A02INA0 T32A02INA1 T32A02OUTA T32A02INC0 T32A02INC1... -
Page 11: Table 3.3 Signal Connection List (3/5)
TXZ+ Family TMPM4K Group(1) Input/Output Ports Table 3.3 Signal Connection List (3/5) Function pin Port M4K4 M4K2 M4K1 Related reference manual name name (LQFP64) (LQFP48) (LQFP44) AINA11/ AINB11 AINA12/ AINB12 AINA10/ AINB10 AINA09/ AINB09 AINA08/ AINB08 AINA07/ AINB07 12-bit Analog to Digital Convertor AINA06/ AINB06... -
Page 12: Table 3.4 Signal Connection List (4/5)
TXZ+ Family TMPM4K Group(1) Input/Output Ports Table 3.4 Signal connection list (4/5) Function pin Port M4K4 M4K2 M4K1 Related reference manual name name (LQFP64) (LQFP48) (LQFP44) EMG0 OVV0 Advanced Programmable PMD0DBG Motor Control Circuit EMG1 PMD1DBG ENC0A ENC0B ENC0Z Advanced Encoder Input Circuit (32-bit) ENC1A ENC1B... -
Page 13: Table 3.5 Signal Connection List (5/5)
TXZ+ Family TMPM4K Group(1) Input/Output Ports Table 3.5 Signal connection list (5/5) Function pin Port M4K4 M4K2 M4K1 Related reference manual name name (LQFP64) (LQFP48) (LQFP44) TRGIN0 Product Information TRGIN1 (Trigger Selector) TRGIN2 Debug Interface (JTAG/SW) TRST_N SWDIO SWCLK TRACECLK TRACEDATA0 Debug Interface TRACEDATA1... -
Page 14: Registers
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4. Registers The following registers should be set to use the port. Each register is 32 bits. The configuration of the register depends on the port count and its function assignment. "x" and "n" in the following table show a port name and a function number, respectively. Register name Type Setting value... -
Page 15: List Of Registers
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.1. List of Registers When the bit which is not assigned is read, "0" is read. The write to it is ignored. Table 4.1 Base Address of Port Registers Peripheral function Channel/Unit Base address 0x400C0000 0x400C0100 0x400C0200... -
Page 16: Table 4.2 List Of Registers
TXZ+ Family TMPM4K Group(1) Input/Output Ports Table 4.2 List of Registers Address Register name Port A Port B Port C Port D Port E Port F (Base+) Data Register 0x0000 [PADATA] [PBDATA] [PCDATA] [PDDATA] [PEDATA] [PFDATA] Output Control Register 0x0004 [PACR] [PBCR] [PCCR]... -
Page 17: List Of Port Function Register Settings
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2. List of Port Function Register Settings It is explained about viewpoint of a list of the port function register settings tables. The column of [PxFRn] shows the function register which should be set. When this register is set to "1", the corresponding function is enabled. -
Page 18: Port A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.2. PORT A Table 4.3 Port A Register Settings Reset status Control register Port PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input Port Input Output Port Output INT07a Input FTU4a UT1TXDA... -
Page 19: Port B
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.3. PORT B Table 4.4 Port B Register Settings Reset status Control register Port PORT Input/Output type Function [PBDATA] [PBCR] [PBFRn] [PBOD] [PBPUP] [PBPDN] [PBIE] After reset Input Port Input Output Port Output INT02a Input FTU4a UT1TXDA... -
Page 20: Port C
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.4. PORT C Table 4.5 Port C Register Settings Reset status Control register Port PORT Input/Output type Function [PCDATA] [PCCR] [PCFRn] [PCOD] [PCPUP] [PCPDN] [PCIE] After reset Input Port Input Output Port Output INT08 Input FTU4a UT3TXDA... -
Page 21: Port D
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.5. PORT D Table 4.6 Port D Register Settings Reset status Control register Port PORT Input/Output type Function [PDDATA] [PDCR] [PDFRn] [PDOD] [PDPUP] [PDPDN] [PDIE] After reset Input Port Input Output Port Output AINA11/ Input FTU5a AINB11 (Note) -
Page 22: Port E
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.6. PORT E Table 4.7 Port E Register Settings Reset status Control register Port PORT Input/Output type Function [PEDATA] [PECR] [PEFRn] [PEOD] [PEPUP] [PEPDN] [PEIE] After reset Input Port Input Output Port Output AINA05/ Input FTU5a AINB05 (Note) -
Page 23: Port F
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.7. PORT F Table 4.8 Port F Register Settings Reset status Control register Port PORT Input/Output type Function [PFDATA] [PFCR] [PFFRn] [PFOD] [PFPUP] [PFPDN] [PFIE] After reset Input Port Input Output Port Output T32A04OUTA Output FTU1a [PFFR4]... -
Page 24: Port G
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.8. PORT G Table 4.9 Port G Register Settings Reset status Control register Port PORT Input/Output type Function [PGDATA] [PGCR] [PGFRn] [PGOD] [PGPUP] [PGPDN] [PGIE] After reset Input Port Input Output Port Output INT04 Input FTU4a UT2TXDA... -
Page 25: Port H
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.9. PORT H Table 4.10 Port H Register Settings Reset status Control register Port PORT Input/Output type Function [PHDATA] [PHCR] [PHFRn] [PHOD] [PHPUP] [PHPDN] [PHIE] After reset Input Port Input Input FTU11a EHCLKIN Input FTU11a After reset Input Port... -
Page 26: Port J
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.10. PORT J Table 4.11 Port J Register Settings Reset status Control register PORT PORT Input/Output type Function [PJDATA] [PJCR] [PJFRn] [PJOD] [PJPUP] [PJPDN] [PJIE] After reset Input Port Input Output Port Output Output FTU2a [PJFR5] SCOUT... -
Page 27: Port K
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.11. PORT K Table 4.12 Port K Register Settings Reset status Control register PORT PORT Input/Output type Function [PKDATA] [PKCR] [PKFRn] [PKOD] [PKPUP] [PKPDN] [PKIE] After reset Input FTU2a [PKFR7] (TDI) Input Port Input Output Port Output INT00a... -
Page 28: Port L
TXZ+ Family TMPM4K Group(1) Input/Output Ports 4.2.12. PORT L Table 4.13 Port L Register Settings Reset status Control register Port PORT Input/Output type Function [PLDATA] [PLCR] [PLFRn] [PLOD] [PLPUP] [PLPDN] [PLIE] After reset Input Port Input Output Port Output NBDDATA0 Input/Output FTU2c [PLFR6]... -
Page 29: Port Circuit Diagram
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5. Port Circuit Diagram The port has 8 types of circuits, FTU1a to FTU5a, FTU11a and FTU16a. Each circuit diagram is shown in the following page and after. The dot line block shows "Equivalent Circuit" which is described in "Datasheet". The "I/O Reset"... -
Page 30: Type Ftu1A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.1. Type FTU1a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) [PxFRn] (Function control) Function output Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Function input Figure 5.1 Port Type FTU1a 30 / 40 2024-07-22... -
Page 31: Type Ftu2A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.2. Type FTU2a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Output function enable [PxFRn] (Function control) Function output Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Function input Figure 5.2 Port Type FTU2a 31 / 40... -
Page 32: Type Ftu2C
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.3. Type FTU2c I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Output function enable [PxFRn] (Function control) Function output Port [PxDATA] Input/Output (Output latch) [PxOD] Open-drain control [PxIE] (Input control) Port read Function Input Figure 5.3 Port Type FTU2c 32 / 40... -
Page 33: Type Ftu3A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.4. Type FTU3a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) [PxFRn] (Function control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Noise filter Function input (30ns Typ.) Figure 5.4 Port Type FTU3a 33 / 40... -
Page 34: Type Ftu4A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.5. Type FTU4a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Noise filter Function input (30ns Typ.) Figure 5.5 Port Type FTU4a 34 / 40 2024-07-22 Rev. -
Page 35: Type Ftu5A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.6. Type FTU5a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Analog input Port read Figure 5.6 Port Type FTU5a 35 / 40 2024-07-22 Rev. -
Page 36: Type Ftu11A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.7. Type FTU11a I/O reset [PxPDN] (Pull-down control) Port External clock input enable Input ([CGOSCCR]<EOSCEN> = 10) [PxIE] (Input control) Port read EHCLKIN Oscillation circuit Figure 5.7 Port Type FTU11a 36 / 40 2024-07-22 Rev. -
Page 37: Type Ftu16A
TXZ+ Family TMPM4K Group(1) Input/Output Ports 5.8. Type FTU16a RESET_N [PxPUP] (Pull up control) [PxPDN] (Pull down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) BOOT_N Figure 5.8 Port Type FTU16a 37 / 40 2024-07-22 Rev. -
Page 38: Precaution
TXZ+ Family TMPM4K Group(1) Input/Output Ports 6. Precaution 6.1. Pin Status During Reset Period During the reset period, the pin status is high impedance except for below pins. And, the pull-up/pull-down is disabled. ● The debug interface alternate pins (PK0 to PK4) are used as debug pins. ●... -
Page 39: Revision History
TXZ+ Family TMPM4K Group(1) Input/Output Ports 7. Revision History Table 7.1 Revision History Revision Date Description 2024-07-22 - First release 39 / 40 2024-07-22 Rev. 1.0... -
Page 40: Restrictions On Product Use
Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"...
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