Hameg HMC8012 Programmer's Manual page 16

SCPI Commands HMC8012
Bit No. Meaning
0...1 Not used
2 Error Queue
The bit is set when an error is occured. If this bit is enabled by the SRE, each entry of the error
queue generates a service request. Thus an error can be recognized and specified in greater detail
by polling the error queue. The poll provides an informative error message. This procedure is to be
S C P I P r o g r a m m e r s M a n u a l
recommended since it considerably reduces the problems involved with remote control.
3 QUEStionable status sum bit
The bit is set, if an EVENt bit is set in the QUEStionable status register and the associated ENABle
bit is set to 1. A set bit indicates a questionable instrument status, which can be specified in detail
S C P I P r o g r a m m e r s M a n u a l
S C P I P r o g r a m m e r s M a n u a l
by polling the QUEStionable status register.
4 MAV bit (message available)
The bit is set, if a readable message in the output buffer is available. This bit can be used to enable
data to be automatical read from the instrument.
5 ESB bit
Sum bit of the event status register. It is set, if one of the bits in the event status register is set and
enabled in the event status enable register. Setting of this bit indicates a serious error, which can be
specified in greater detail by polling the event status register.
6 MSS bit (master status summary bit)
The bit is set, if the instrument triggers a service request. This is the case, if one of the other bits of
this register is set together with its mask bit in the service request enable register SRE.
OPERation status register sum bit
7
The bit is set, if an EVENt bit is set in the OPERation status register and the associated ENABle bit
is set to 1. A set bit indicates that the instrument is just performing an action. The type of action can
be determined by polling the OPERation status register.
Table 1.8: Bits of the status byte (please refer to page 20)
Event Status Register (ESR) and Event Status Enable Register (ESE)
:ACQuire
The ESR is defined in IEEE 488.2. It can be compared with the EVENt part of a SCPI register. The event status register
can be read out using command *ESR?.
:CHAN1OFFSet
The ESE corresponds to the ENABle part of a SCPI register. If a bit is set in the ESE and the associated bit in the ESR
changes from 0 to 1, the ESB bit in the STB is set. The ESE register can be set using the command
using the command *ESE?.
HAMEG Instruments GmbH • Industriestr. 6 • D-63533 Mainhausen • Deutschland
HAMEG Instruments GmbH • Industriestraße 6 • D-63533 Mainhausen
HAMEG Instruments GmbH • Industriestraße 6 • D-63533 Mainhausen
Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: info@hameg.com Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: info@hameg.com
Tel.: +49 (0) 6182 800 0 • Fax: +49 (0) 6182 800 100 • E-Mail: info@hameg.com
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Geschäftsführer: Dipl.-Ing. Holger Asmussen • AG Offenbach am Main HRB 41200
Geschäftsführer: Dipl.-Ing. Holger Asmussen • AG Offenbach am Main HRB 41200
:DISPlay
:HCOPy
*ESR?
H M O S e r i e s
H M S S e r i e s
H M S S e r i e s
Firmware Version: 01.020 and later
Firmware Version: 01.020 and later
Firmware Version: 03.00 and later
:MEASure
:LOGic:SIZE
*OPC?
HMO352x, HMO2524
HMO72x ... HMO202x
:POD1
:SYSTem
*ESE
and read
*SRE?
Subject to change without notice
Subject to change without notice
Subject to change without notice
English
English
English
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