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Technical Manual
5.5.12. Connector X1406 (Debug Interface)
CPU_SOUT1
Transmitter serial data output from serial port (LVTTL).
CPU_SIN1
Receiver serial data input (LVTTL).
DDC_SCL, DDA_SDA
These two pins are functionally suitable for a DDC interface between the graphics controller chip and the
CRT monitor. Open collector bidirectional signals with TTL level (pulled up).
BBATT
3V backup cell input. BATT should be connected to a 3V backup cell for RTC operation and storage
register non-volatility in the absence of system power. (VBATT = 2.4 - 3.3V DC)
5.5.13. Connector X903 (FLEX32 Interface)
All signals are LVTTL compatible.
PR0-PR5
Red color data lines for flatpanel.
PG0-PG5
Green color data lines for flatpanel.
PB0-PB5
Blue color data lines for flatpanel.
PCLK
Data shift clock for flatpanel.
PHS
Horizontal sync pulse for flatpanel.
PVS
Vertical sync pulse for flatpanel.
PDE
Data enable signal for flatpanel.
Panel_VCC
Switched Power supply for flatpanel. Caution: adjust correct voltage setting with J906
R/L
Rotate image in right or left direction (only panel feature). Adjust correct setting with J909
U/D
Rotate image up or down (only panel feature). Adjust correct setting with J908
ePanel-mgx
Page 23 of 45 Pages
Connector locations and pinouts
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