Rabbit RabbitCore RCM2200 User Manual page 61

Figure A-4 shows a typical timing diagram for the Rabbit 2000 microprocessor external
I/O read and write cycles.
A[15:0]
/IOCSx
/IORD
/BUFEN
D[7:0]
A[15:0]
/IOCSx
/IOWR
/BUFEN
D[7:0]
Figure A-4. External I/O Read and Write Cycles—No Extra Wait States
T is the time required for the address output to reach 0.8 V. This time depends on the
adr
bus loading. T is the data setup time relative to the clock. Tsetup is specified from
setup
30%/70% of the V
DD
User's Manual
External I/O Read (no extra wait states)
T1
CLK
T adr
/CSx
T CSx
T IOCSx
External I/O Write (no extra wait states)
T1
CLK
T adr
/CSx
T CSx
T IOCSx
voltage level.
Tw T2
valid
T CSx
T IOCSx
T IORD T IORD
T BUFEN
T BUFEN
T setup
T hold
Tw T2
valid
T CSx
T IOCSx
T IOWR
T IOWR
T BUFEN T BUFEN
valid
T DHZV T DVHZ
valid
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