Clock Source; Reset Source; Table 3. 32.786 Khz Crystal X1 Related Solder Bridges; Table 4. 25 Mhz Crystal X2 Related Solder Bridges - STMicroelectronics STM32439I-EVAL User Manual

UM1668
2.3

Clock source

Two clock sources are available on the STM32439I-EVAL evaluation board for the
STM32F439NIH6 and embedded RTC.
The camera module, Ethernet PHY and USB PHY on the STM32439I-EVAL evaluation
board have their own clock sources.
•
X1, 32.768 KHz crystal for embedded RTC.
•
X2, 25 MHz crystal with socket for STM32F439NIH6 microcontroller, it can be removed
from the socket when an internal RC clock is used.
•
X3, 24 MHz oscillator for camera module.
•
X4, 25 MHz crystal with socket for Ethernet PHY.
•
X5, 24 MHz crystal for USB OTG2 HS PHY.
Solder bridge
SB3
SB4
Solder bridge
SB5
SB6
Jumper JP6 for Ethernet clock refer to
2.4

Reset source

The reset signal of STM32439I-EVAL evaluation board is low active. Reset sources include:
•
Reset button B1
•
Debugging tools from JTAG/SWD connector CN16 and ETM trace connector CN13
•
Daughterboard from CN6
•
Embedded ST-LINK/V2

Table 3. 32.786 KHz crystal X1 related solder bridges

Description
PC14 is connected to 32.786 KHz crystal when SB3 is open. (Default setting)
PC14 is connected to extension connector CN7 when SB3 is closed. In such case
R19 must be removed to avoid disturbance due to the 32.786 KHz quartz.
PC15 is connected to 32.786 KHz crystal when SB4 is open. (Default setting)
PC15 is connected to extension connector CN7 when SB4 is closed. In such case
R18 must be removed to avoid disturbance due to the 32.786 KHz quartz.

Table 4. 25 MHz crystal X2 related solder bridges

Description
PH0 is connected to 25 MHz crystal when SB5 is open. (Default setting)
PH0 is connected to extension connector CN6 when SB5 is closed. In such case
R20 must be removed to avoid disturbance due to the 25 MHz quartz
PH1 is connected to 25 MHz crystal when SB6 is open (Default setting).
PH1 is connected to extension connector CN7 when SB6 is closed. In such case
C23 & X2 must be removed to avoid disturbance due to the 25 MHz quartz.
DocID025151 Rev 2
Hardware layout and configuration
Section 2.13.
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