Auxiliary Power; Output Stage; Digital Circuit - Chroma 62000P Series Operating & Programming Manual

Programmable dc power supply
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Programmable DC Power Supply 62000P Series Operating & Programming Manual
6.2.2

Auxiliary Power

1.
The input terminal of auxiliary power is AC source (after EMI filter but before PFC relay
and fuse) goes through the bridge rectifier and passes the flyback converter to get the
desired output voltage. The PWM IC used is Unitrode UC3845.
2.
The output of auxiliary power is divided into three types of isolate power and they are
named PGND, OGND and DGND based on their potential. The PGND is to input PFC
and primary side reference potential of output stage, while OGND is the secondary side
reference potential of output stage and DGND is the reference potential of digital signal
and communication interface.
6.2.3

Output Stage

1.
The output stage structure is full bridge that uses Unitrode UC3525 as PWM IC and
controlled under voltage mode.
2.
There are two output modes -- Constant Voltage (CV Mode) and Constant Current (CC
Mode) that switches automatically according to load state.
In Constant Voltage mode, following controls the IC detecting signal:
(1) Output voltage;
(2) The load actual voltage (remote sense) through output line, in which the remote
sense can be disconnected but the accuracy will drop.
In Constant Current mode, following controls the IC detecting signal:
(1) Output current.
3.
The secondary side is two stages LC filter to lower down ripple voltage and ripple
current.
4.
Dummy load is near to no load only at output and acts when the programmed voltage is
less than the present output. It is treated as constant current source when acts with 1
Amp fixed loading. When the output voltage and set value is less than 3% the dummy
load will disable automatically. The output has OVP and when it exceeds the OVP
voltage (12 bit DAC) set by the front panel, the output will be disabled.
5.
There is no current sharing function when connecting in parallel. When in parallel state
the OVP set for lower output voltage will close automatically. Only the OVP set to its
maximum will be enabled to avoid error action.
6.2.4

Digital Circuit

1.
The digital circuit control unit is composed of Philips XA-G3 microprocessor with Xilinx
FPGA (Spartan II, XC2S15) and CPLD (9572).
2.
The power source 3.3V and 2.5.V required by FPGA is got from +5V.
3.
The signal of analog program interface and digital circuit are isolated by the power
source of +12VD with the free-run flyback converter and linear regulator.
4.
The TTL output is +5V level and the internal digital signal is +3.3V level, therefore there
are actions for level change.
6-4

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