Table of Contents
Advertisement
BL600-Sx Hardware Integration Guide
Single Mode BLE Module
6 H
I
ARDWARE
NTEGRATION
6.1 Circuit
The BL600-series module is easy to integrate requiring no external components on the customer's board apart
from those required by customer for development and in customers end application.
Checklist (for Schematic):
VCC
External power source within the operating range, rise time and noise/ripple specification of BL600.
Add decoupling capacitors for filtering the external source. Power-on reset circuitry within BL600 series
module incorporates brown-out detector, thus simplifying power supply design. Upon application of
power, the internal power-on reset ensures module starts correctly.
VCC and coin-cell operation
With built-in DCDC (operating range 2.1V to 3.6V), reduces the peak current required from a coin-cell
(CR2032), making it easier to use with coin-cell.
AIN (ADC) and SIO pin IO voltage levels
BL600 SIO voltage levels are at VCC. Ensure input voltage levels into SIO pins are at VCC also (if VCC
source is a battery whose voltage will drop). Ensure ADC pin maximum input voltage for damage is not
violated.
AIN (ADC) impedance and external voltage divider setup
If one wanted to measure with ADC, a voltage higher than 3.6V then then one can connect a high
impedance voltage divider to lower the voltage to the ADC input pin. Other methods are to use a
voltage buffer or FET transistor in conjunction with a low resistance voltage divider.
High impedance values of a voltage divider connected to an AIN pin will introduce ADC inaccuracy.
Laird recommends the following solution for setup of a voltage divider when used with the BL600 ADC:
Connect a capacitor between AIN and ground (if the voltage divider presents high impedance).
-
Normally, when ADC is not sampling, the ADC (AIN) impedance is a very high value and can be
considered an open circuit. The moment ADC is sampling, ADC (AIN) impedance is 200k-600k and
lowers the AIN voltage. However, when the capacitor is connected it should keep the AIN voltage at
previous level for an adequate time period while sampling, minimizing the effect of the high
resistance value of the external voltage divider. The capacitor should be big enough to hold voltage
up for the required time period, i.e. 20 us for 8 bit sampling or 68 us for 10 bit sampling. If you use
a FET transistor to open the current flow through the circuit momentarily before sampling, allow
enough time for the capacitor to fully charge before sampling. During the sampling period, multiple
samples are made and the ADC output value is the mean value from the sample pool. As noted in
Table 6
the sample pool is created during 20 us period for 8 bit sampling, 36 us period for 9 bit
sampling and 68 bit period for 10 bit sampling.
JTAG
smart
Is required if
releases from Laird), then add JTAG connector and 12K resistor to GND as detailed in section
Miscellaneous (hidden JTAG)
Note: Customers
UART
Is required for loading customer
upgrade). Add connector to allow UART to be interfaced to PC (via UART –RS232 or UART- USB).
Americas: +1-800-492-2320 Option 2
Europe: +44-1628-858-940
Hong Kong: +852-2923-0610
www.lairdtech.com/bluetooth
S
UGGESTIONS
BASIC runtime engine FW upgrade capability is required (to upgrade to future /later
fit the 12K resistor on their host board when using the BL600-Sx-04.
MUST NOT
smart
BASIC application script during development (or for subsequent
31
CONN-HIG-BL600
Advertisement
Table of Contents
