Xilinx KC724 IBERT Getting Started Manual page 9

All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors.
pad.
X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the GTX transceiver reference
clocks in the IBERT demonstrations.
SMA connectors on the clock module which can be connected to the reference clock cables.
Note:
board.
X-Ref Target - Figure 1-3
SI570_CLK_P
SI570_CLK_N
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note:
SuperClock-2 module.
For the GTX IBERT demonstration, the output clock frequencies are preset to 125.000 MHz.
For more information regarding the SuperClock-2 module, refer to UG770,
HW-CLK-101-SCLK2 SuperClock-2 Module User Guide.
KC724 IBERT Getting Started Guide
UG931 (v1.0) October 23, 2012
Figure 1-2 shows the connector pinout.
B
A
GTX Connector Pad
Figure 1-2: A – GTX Connector Pad. B – GTX Connector Pinout
The image in Figure 1-3 is for reference only and might not reflect the current revision of the
CLKOUT1_P
CLKOUT1_N
The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
www.xilinx.com
Running the GTX IBERT Demonstration
Figure 1-2
B
P
P
P
P
P
GTX Connector Pinout
Figure 1-3 shows the locations of the differential clock
CLKOUT2_P CLKOUT3_P
CLKOUT2_N CLKOUT3_N
shows the connector
A
GTX
P
N
N
N P
N
P
N
N
P
N
N
P
N
N
UG931_c1_02_080812
CLKOUT4_P
CLKOUT4_N
UG931_c1_03_080812
9