Advertisement
Clock Synthesizer
Notes:
- Place all decoupling caps as close to VCC/GND pins as possible
- PCI_0/ICH pin has to go to the ICH.
(This clock cannot be turned off through SMBus)
- CPU_ITP pin must go to the ITP. It is the only
CPU CLK that can be shut off through the SMBUS interface.
A
VCC3_3
Q29
F D N 3 5 9 AN
33 VTTPWRGD12
VCC_CLOCK
VCC_CLOCK
L4A
1
2
C11A
C12A
C13A
22UF
0.1UF
.001UF
31
FMOD1
C21A
R31A
REFCLK
14
ICH_CLK14
10
14
ICH_3V66
R35A
8
GMCH_3V66
13
PCLK_0/ICH
R40A
17
PCLK_1
17
PCLK_2
R44A
18
PCLK_3
16
PCLK_4
R48A
18
PCLK_5
VCC3_3
15
PCLK_6
14,16
SIO_CLK24
14,16
USBCLK
R53A
L5A
9
DOTCLK
BC22
BC23
X10PF
X10PF
L_CKVDDA
C22A
C23A
0.1UF
.001UF
APIC Clk Strap JP20A
16 MH z
33 MH z
A
USBV3
C4A
C5A
22UF
0.1UF
PCIV3
C15A
C16A
C6A
C14A
0.1UF
.001UF
.1UF
.001UF
U2A
C20A
Y1A
12PF
XTAL_IN
3
XTAL_IN
14.318MHZ
REF
4
XTAL_OUT
XTAL_OUT
12PF
1
REF0
R33A
3V66_0
7
3V66_0
22
3V66
3V66_1
8
3V66_1
22
CK810e
R38A
11
PCI_0/ICH
33
12
PCI_1
R42A
33
13
PCI_2
33
15
PCI_3
PCI
R46A
PCI_3
33
16
PCI_4
33
18
PCI_5
R49A
33
19
PCI_6
33
20
PCI_7
R52A
25
USB_0
33
USB
26
USB_1
22
22
V D D _ A
23
VSS_A
Minimize Stub Length from
J P 1 A
CLK14 trace to
JP20A.
R54A
in
10K
o u t
A
VCC_CLOCK
L2A
1
2
1
MEMV3
C7A
C8A
C9A
C10A
C17A
C18A
.001UF
.1UF
.001UF
0.1UF
.001UF
0.1UF
R26A
8.2K
R27A
55
APIC_0
APIC_0
33
R28A
APIC
54
APIC_1
APIC_1
33
R29A
52
CPU_0_1
CPU_0
R30A
33
50
CPU
CPU_1
R32A
33
49
CPU_2
CPU_2/ITP
33
R34A
MEMCLK0
46
DRAM_0
SDRAM_0
R36A
22
MEMCLK1
45
DRAM_1
SDRAM_1
R37A
22
MEMCLK2
43
DRAM_2
SDRAM_2
R39A
22
MEMCLK3
42
DRAM_3
SDRAM_3
R41A
22
MEMCLK4
40
DRAM_4
SDRAM_4
R43A
22
MEMCLK5
39
DRAM_5
SDRAM_5
22
R45A
MEMCLK6
37
DRAM_6
Memory
SDRAM_6
R47A
22
MEMCLK7
36
DRAM_7
SDRAM_7
22
R50A
34
D C L K
D C L K
22
R 5 1 A
32
P W R D W N #
10
31
S C L K
30
SDATA
29
SEL1
28
SEL0
51
VDD2_5[0]
L_VCC2_5
53
VDD2_5[1]
C24A
C25A
C26A
56
VSS2_5[1]
48
.001UF
0.1UF
4.7UF
VSS2_5[0]
Title:
Intel® 810e2 Chipset Universal Socket 370 CRB
IAMG Platform Apps Engineering
int e l
1900 Prairie City Road
Folsom, Ca. 95630
VCC_CLOCK
L 3 A
2
C19A
22UF
R 3 4 7
0
APICCLK_CPU 4
R 3 4 8
130
TUAL5 33
APICCLK_ICH 13
Q28
2 N 7 0 02
CPUHCLK
4
GMCHHCLK 7
ITPCLK
4
MEMCLK[7:0] 11,12
A
DCLK_WR
8
VCC2_5
SLP_S3#
14,16,30
CK_SMBCLK 25
CK_SMBDATA 25
L6A
FREQSEL
9,31
REV.
1.0
Clock Synthesize r
Last Revision Date :
9/02/01
Sheet:
6
of
36
Advertisement
