Aintc System Interrupt Assignments - Texas Instruments AM1802 Reference Manual

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SPRUGX5A – May 2011
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Table 11-1. AINTC System Interrupt Assignments
Interrupt Name
COMMTX
COMMRX
NINT
—
EDMA3_0_CC0_INT0
EDMA3_0_CC0_ERRINT
EDMA3_0_TC0_ERRINT
EMIFA_INT
IIC0_INT
MMCSD0_INT0
MMCSD0_INT1
PSC0_ALLINT
RTC_IRQS[1:0]
SPI0_INT
T64P0_TINT12
T64P0_TINT34
T64P1_TINT12
T64P1_TINT34
UART0_INT
—
PROTERR
SYSCFG_CHIPINT0
SYSCFG_CHIPINT1
SYSCFG_CHIPINT2
SYSCFG_CHIPINT3
EDMA3_0_TC1_ERRINT
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
DDR2_MEMERR
GPIO_B0INT
GPIO_B1INT
GPIO_B2INT
GPIO_B3INT
GPIO_B4INT
GPIO_B5INT
GPIO_B6INT
GPIO_B7INT
GPIO_B8INT
—
UART_INT1
MCASP_INT
Copyright © 2011, Texas Instruments Incorporated
Source
ARM
ARM
ARM
Reserved
EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
EDMA3_0 Channel Controller 0 Error Interrupt
EDMA3_0 Transfer Controller 0 Error Interrupt
EMIFA Interrupt
I2C0 interrupt
MMCSD0 MMC/SD Interrupt
MMCSD0 SDIO Interrupt
PSC0 Interrupt
RTC Interrupt
SPI0 Interrupt
Timer64P0 Interrupt (TINT12)
Timer64P0 Interrupt (TINT34)
Timer64P1 Interrupt (TINT12)
Timer64P1 Interrupt (TINT34)
UART0 Interrupt
Reserved
SYSCFG Protection Shared Interrupt
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
SYSCFG CHIPSIG Register
EDMA3_0 Transfer Controller 1 Error Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
DDR2 Controller Interrupt
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
GPIO Bank 6 Interrupt
GPIO Bank 7 Interrupt
GPIO Bank 8 Interrupt
Reserved
UART1 Interrupt
McASP0 Combined RX/TX Interrupt
ARM Interrupt Controller (AINTC)
Interrupt Mapping
219