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A.3 J3 Connector Pinout
42 VMICPCI-7055/CPCI-7055RC Hardware Reference Manual
Table A-2 J2 Connector and Pinout
Pin
Row A
Row B
No.
1
CPCI_CLK
GND
1
* VCC_VIO - The VMICPCI-7055/CPCI-7055RC are universal VIO designs.
The VMICPCI-7055/CPCI-7055RC support a 64-bit CompactPCI bus.
The J3 connector is a five row, 19 pins each, 2 mm "Hard Metric" CompactPCI
connector. An additional external metal shield is also used, labeled row F. Figure
below illustrates the J3 connector and the connector pinout. This connector is used
to route the two serial ports and the two Gigabit Ethernet ports to the backplane
rear I/O.
Table A-3 J3 Connector and Pinout
Pin
Row A
Row B
No.
19
GND
GND
18
LPA_BI_DA+
LPA_BI_DA
2-
17
LPA_BI_DB+
LPA_BI_DB
2-
16
LPB_BI_DA+
LPB_BI_DA
2-
15
LPB_BI_DB+
LPB_BI_DB
2-
14
GND
GND
13
SP2_RTS
SP1_RI
12
SP1_RTS
SP2_DTR
11
SP2_TXB
SP2_RXD
10
SP1_TXB
SP1_RXD
9
GND
GND
8
LPA_BI_DA2
LPA_BI_DA
+
2-
7
LPA_BI_DB2
LPA_BI_DB
+
2-
6
LPB_BI_DA2
LPB_BI_DA
+
2-
5
LPB_BI_DB2
LPB_BI_DB
+
2-
4
GND
GND
3
G1_Y_LINK1
G1_G_LK10
00#
00#
2
G1_G_LINK1
G1_Y_ACT
0#
Row C
Row D
CPCI_REQ1# CPCI_GNT1# CPCI_REQ2#
Row C
Row D
GND
GND
GND
LPA_BI_DC+
GND
LPA_BI_DD+
GND
LPB_BI_DC+
GND
LPB_BI_DD+
GND
GND
SP2_DSR
SP2_DCD
VCC_5.0
SP1_CTS
SP1_DTR
SP1_DCD
SP1_DSR
SP2_RI
N/C
GND
SP2_ACTIV
LPA_BI_DC2+
E
SP2_LOOPB
LPA_BI_DD2+
ACK
SP2_R485/
LPB_BI_DC2+
232
SP1_ACTIV
LPB_BI_DD2+
E
VCC_5.0
GND
SP1_R485/
GND
232
SP1_LOOPB
G2_Y_LINK100
ACK
#
Row E
Row
Row E
F
GND
GND
LPA_BI_DC-
GND
LPA_BI_DD-
GND
LPB_BI_DC-
GND
LPB_BI_DD-
GND
GND
GND
SP2_CTS
GND
GND
GND
LPA_BI_DC-
GND
LPA_BI_DD2
GND
-
LPB_BI_DC2
GND
-
LPB_BI_DD2
GND
-]
GND
GND
GND
GND
N/C
GND
VCC_3.3
GND
VCC_3.3
GND
G2_G_LK10
GND
00#
Publication No. 500-657055-000 Rev. G
Row
F
GND
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