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3 • Embedded PC/RTOS Features
3.1 CompactPCI Bus Bridge
Publication No. 500-657055-000 Rev. G
The VMICPCI-7055/CPCI-7055RC feature additional capabilities beyond those of
a typical desktop computer system. The unit provides standard general-purpose
timers along with a programmable Watchdog Timer for synchronizing and
controlling multiple events in embedded applications. The VMICPCI-7055/
CPCI-7055RC also provide support for a CompactFlash disk system or PICMG
2.16 Ethernet over the CompactPCI backplane or rear I/O using the
VMIACC-7055/ACC-7055RC RTMs. PICMG 2.9 support is available, which
allows for compatibility with the most demanding CompactPCI applications.
These features make the unit ideal for embedded applications, particularly where
standard hard drives and floppy disk drives cannot be used.
The VMICPCI-7055/CPCI-7055RC incorporate a PLX PCI-6254 (Hint HB6AB)
Universal Bridge device that performs universal PCI bridging functions for
embedded and intelligent I/O applications. The PCI device acts as a gateway to an
intelligent subsystem. As a peripheral controller it allows the local
VMICPCI-7055/CPCI-7055RC processors to configure and control the onboard
local subsystem independent from the CompactPCI bus host processor. The
VMICPCI-7055/CPCI-7055RC local PCI subsystem is presented to the
CompactPCI bus host as a single CompactPCI device. As a system controller, the
bridge acts as a standard transparent PCI-to-PCI bridge. For detailed information
concerning the embedded PCI bus bridge, consult the PLX PCI-6254 (Hint HB6)
datasheet.
The VMICPCI-7055/CPCI-7055RC PCI bridge device provides the following
features:
3.1.1 PCI Interface
• Full compliance with the PCI Local Bus Specification, Revision 2.2
• Supports 3.3 V or 5 V VIO operation
• Concurrent local (secondary) and CompactPCI (primary) bus operation
3.1.2 Buffer Architecture
• Queuing of multiple transactions in either direction
• 256 byte of posted write (data and address) buffering in each direction
• 256 byte of read data buffering in each direction
• Four delayed transaction entries in each direction
3.1.3 Blade Mode
This mode disables the bridge to the backplane. This results in the ability to be
inserted into any slot on the backplane, with or without a system controller. All
PCI signals from the chassis will be ignored. PIGMG 2.16 will still be available on
the backplane.
Embedded PC/RTOS Features 37
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